1. Embedded Hardware Peripherals Development tools
Embedded Systems Software Training Center
Embedded Hardware Peripherals Development tools
COPYRIGHT © 2016 DSR CORPORATION

2. Instructor Introduction
Matveev Alexey Igorevich
Senior software developer,
DSR corp.
Copyright © 2015 DSR Corporation

3. Summary Embedded Hardware Peripherals Development Environment
Peripheral devices
Interrupts and external events
Exceptions
Development Environment
Copyright © 2016 DSR Corporation

4. Objectives Understand computer peripherals basics
Understand interrupt handling basics
Understand development environment
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5. Class Materials
Embedded Hardware Basics diagrams and Hands-on Exercises are available on
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6. Peripheral Devices COPYRIGHT © 2016 DSR CORPORATION

7. Peripheral Devices CPU RAM ROM GPIO Timer
Peripheral is the way of how computer (embedded system) interfaces the real world. A peripheral is a device attached to a host computer, but does not form part of the core. It expands the host's capabilities.
Common peripheral devices
GPIO (General Purpose I/O), parallel I/O, serial I/O
Timers, DMA
CPU
Memory
Peripherals
CPU
RAM
ROM
GPIO
Timer
Control
Address
Data
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8. Device Registers CPU CPU
CPU registers are used for calculation and controlling CPU.
To interact with a peripheral device a CPU uses device registers.
Common device registers for peripheral devices:
Control register, selects the mode of operation of the device
Status register, shows operating mode, current device status, errors
Data register, to perform data i/o
Device registers
Device register
GPIO
GPIO
CPU
Port Direction
Timer Mode
CPU
Port Data
Counter … …
Control
Data
Address
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9. Peripheral Device Access
Memory address mapped IO operations
The CPU has common address space for IO devices and memory
The CPU uses the same input-output and memory load-store instructions
The CPU uses common control signals (control bus) to control the memory and IO devices
0x00000
I/O space
char temp;
/* Write to memory */
*(char *)&temp = 0xBE; …
/* Write to IO device */
*(char *)(0x100) = 0xEF;
Write to memory
Write to IO device
0x00400
Internal RAM
mov.b #BEh, R0
mov.b R0, 0x3000 …
mov.b #EFh, R0
mov.b R0, 0x0100
0x033FF …
0xE0000
Internal ROM
0xFFFFF
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10. Peripheral Device Access (cont.)
Memory address mapped IO operations
The CPU has different address space for IO devices and memory
The CPU uses the different input-output and memory load-store instructions
The CPU uses different control signals (control bus) to control the memory and IO devices
Example: x86, AVR
0x0000
0x0040
System
Memory …
Timer …
0x005F …
mov al, BEh
mov [0x3000], al …
mov al, EFh
out 0x0100, al
Write to memory
0x0060 …
GPIO …
0x006F
Write to IO device …
0x03F8 …
Serial Port
0xFFFF …
0x03FF

11. Counter source select bit
Control Register
The control registers are used to set up different modes
Some features are configured by separate bits
The first step in programming peripheral devices is to understand control registers of the device
Counter source select bit
Timer
A0 mode register
Name
Address
R/W
Access Size
Timer A0 mode register
0x0396 8
Timer A0 register
0x0387 R 16
Counter start flag
0x0380 7 6 5 4 3 2 1
TMOD0
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
Specify the operating mode 00: Timer mode 01: Event counter mode 10: One-shot timer mode 11: Pulse with modulation (PWM) mode
Different functions depending on the mode
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12. GPIO (General Purpose I/O)
GPIO is a single generic pin on a chip whose behavior can be controlled by software
GPIOs are grouped into ports. Typical port width is 8-, 16-, 32- bits.
GPIO ports are differed by numbers or letters (e.g., PORTA, PORTB, …, P0, P1, …)
Every GPIO can be configured to be input
(e.g., button handling) or output(e.g., LED indication):
Port Direction Register (0 – Input, 1 - Output)
GPIO has discrete state – logic “0” or “1”:
Port Register holds current pin state
GPIO control registers:
Pull-Up control registers
Port Control Register
Pin Assignment Control Register
Port Registers
LSI
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13. Pull-up and Pull-down
High and low voltage values (Hi and Lo) are used to determine the ‘1’ and ‘0’ digital value
Example: When the supply voltage is nearly 5v, 4 ~ 5v is Hi, 0 ~ 1v is Lo
Digital signal voltage values must be in the range of Lo or Hi
Pull-up and pull-down
Circuit configuration for stable electrical input when connecting a switch to an input GPIO port
Example of pull-up
Switch ON
Switch OFF
Port Register
Port Register
Switch
Switch
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14. UART serial interface UART = Universal Asynchronous Receive/Transmit
Also known as the “Serial Port” (RS-232)
First applications: Terminals, Printers and Modems
Different protocols use serial I/O
Baud rate (BPS) 9600, 14400, 38400, 57600,
Parity
Number of stop bits
（LSB）
（MSB） 1 …
Start Bit
Data (7-8 bits)
Parity Bit
Stop Bits (1-2)
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15. UART serial interface (cont.)
The “DB-9” configuration contains different signals:
Ground (#5)
TxD - Transmitted Data (#3)
RxD – Received Data (#2)
DTR – Data Terminal Ready (#4)
DSR – Data Set Ready (#6)
RTS – Request To Send (#7)
CTS – Clear To Send (#8)
DCD – Data Carrier Detect (#1)
RI – Ring Indicator (#9)
All we care about are the TX/RX signals:
Ground signal (as reference)
TxD signal as output
RxD signal as input
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16. UART serial interface (cont.)
There are three key interfaces:
Configuration registers:
Configure interrupts, baud rate, parity, etc.
Check the status of the UART
Send register
Write in data byte that need to be sent out
Receive register
Read out data byte that have been received RX
Baud
Rate
Generator
Receiver TX
Transmitter
CPU Interface
Transmission and reception of data can be handled separately and independently
Status/
Control Registers
Modem I/O
Signals …
Sending data:
Wait for transmitter buffer is empty
Write data to TX buffer (register)
Write next data byte
Receiving data:
Wait for receiver buffer is not empty (got some data)
Read data byte
Wait for next “not empty” event

17. SPI Bus SPI stands for Serial Peripheral Interface
It is used for moving data simply and quickly from one device to another
SPI is a synchronous serial Master-Slave protocol
The data is clocked along with a clock signal (SCK).
The clock signal controls when data is changed and when it should be read
The Master device controls the Slave device
No data is transferred unless the Master initiates data transfer
The slave device cannot manipulate SCK signal
SPI is a data exchange protocol
As data is being clocked out, new data is clocked in
Data is exchanged – no device can just be a transmitter only or receiver only
The Master controls the exchange by manipulating the clock line (SCK)
The Master controls the Slave device by asserting the CS or SS signal
CS or SS signal is known as “Chip Select” or “Slave Select” and is frequently an active-low signal

18. SPI Bus (cont.) MOSI – Master Output, Slave Input
MISO – Master Input, Slave Output
SCK – Signal ClocK
CS(SS) – Chip Select (Slave Select)
SCK
SCK
MOSI
MOSI
MISO
MISO
___ __
SS1
___ SS
SS2
Slave 2
SCK
MOSI
MISO __ SS

19. SPI Bus (cont.)
Set specific value to control registers to configure I/O port
Transmitter side: read value to send from special register, put it to transmit the buffer
Often FIFO is used
Receiver side: get received byte from buffer and put it to special register
To check if send or receive complete, check the status register
Master
Slave
Control / status register
Control / status register
Transmit Buffer
Receive buffer
CPU
SCK
CPU
FIFO
FIFO
MOSI 7 6 5 4 3 2 1 1 3 2 5 7 6 4
Shift register
MISO
Shift register
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20. Hardware Timer Timer functions Software timer Hardware Timer
Time measurement
Run periodic process
Detect and count external events
Software timer
Uses CPU time to calculate ticks in the loop
Low accuracy (low resolution, deviations due to cache and bus)
Other processes interacting
Hardware Timer
Hardware measures ticks from input clock. Input clock is determined.
Calculations are made according to the input clock that counts with high accuracy
Processor time is not used
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21. Hardware Timer (cont.) Timer counting
Count down. The value of the counter is decremented every clock until a timer reaches the 0 value
Count up. The value is incremented at each clock until a timer reaches a certain value
Auto-Reload
When timeout occurs, the timer function starts
The counter value
Count Down
The counter value
Count up
Timer value
Timer value
Time
Time
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22. Peripheral Device: Hardware Timer (cont.)
Register Configuration
Counter register
Timer value register
Status Register
According to timer configuration count up or down with specified clock source speed
Timeout Notification
Set a particular bit in the status register
Generate an interrupt
Timer value register
Reload (when counting down) Compare (when counting up)
Clock Source
Counter register
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23. External Events COPYRIGHT © 2016 DSR CORPORATION23

24. Waiting For External Events: Poll
Examples of external events:
 Button is pressed, data is received or transmitted, etc.
Polling
When an external event occurs, the corresponding register bit is set in Status Register
Program needs to check the appropriate bit
Check interval
Short interval of checking causes increase in overhead
If long time interval is used for check, a real-time condition is getting low Trade-off: real-time vs. check overhead
Long check interval
Short check interval
Event occurred
Event occurred
Check for the event
Event is found
Workflow
Response time
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25. Waiting For External Events: Interrupt
Idea: accept occurrence of an event asynchronously
Software:
When an event occurs, a processor suspends current process, and predetermined function (interrupt handler) is called to handle the event
Hardware
When a signal is set on a processor's interrupt pin, a value of a PC (Program Counter) is saved and an address value of an interrupt handler is stored into PC
Interrupt is generated
Start
End
Interrupt handler
The main code
Break
Resume
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26. Interrupt Terms
Interrupt – asynchronous requests can be issued from different sources
Each interrupt request is handled in a specific interrupt service routine (ISR)
A processor can accept multiple interrupts
Interrupt response time - time needed to start an ISR. This parameter is critical for embedded systems that require real-time
Interrupt sources:
External, used to request emergency processing
Internal, used for error handling or internal requests processing
Exception examples
Well-known RESET
Zero divide
Page-out, access violation
Bus error, address error
Software interrupt instruction (instruction INT)
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27. Interrupt Priority and Masking
Priority is assigned to each interrupt – is used to handle concurrent interrupt requests
Particular interrupts or all interrupts can be disabled by setting a bit in an Interrupt Mask Register's (IMR) bit-mask
Non-maskable interrupt (NMI) is a hardware interrupt that lacks an associated bit-mask, so that it can never be ignored. NMIs are often used for timers, especially watchdog timers, hardware errors.
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28. Programmable Interrupt Controller (PIC)
Accept multiple interrupt requests, issue a single interrupt request to a processor
Each interrupt request can be configured to be ignored
Interrupt Source Register is used to determine what interrupt occurred
Several PICs can be used in cascade
Get interrupt information
Stores information about interrupt
Interrupt enable/disable
PIC
CPU
Source Register
Mask register
Interrupt request 1
Interrupt request 2
Interrupt request 3
Interrupt request 4
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29. Interrupt Edge-Triggered and Level-Triggered
Interrupt is signaled by a level transition on the line, either a falling edge (high to low) or a rising edge (low to high)
Status register stores interrupt requests
Level-Triggered
The particular state level is considered as interrupt. An interrupt drives the line to its active level, and then holds it at that level until serviced.
The next interrupt can be missed if line remains active.
Rising edge
Falling edge
High level
VCC
Threshold H
Low level
Threshold L
GND
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30. Interrupt Vector
Interrupt vector is used to determine what ISR to start
An interrupt vector is the memory address of an ISR or index into an array called an interrupt vector table
Interrupt vector table stores all ISRs addresses in memory, it’s beginning can be fixed or not
Vector Base
Interrupt vector table
0x00
Interrupt handler Address
0x04
Interrupt handler Address 2
0x08
Interrupt handler Address 3 …
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31. Interrupt Vector
Interrupt vector can contain address of ISR or ISR instructions themselves
Example
SH3: interrupt vector table contains ISR instructions
Reset: 0x000
Exception: Vector Base + 0x100
Interrupt Vector Base + 0x400
ARM: interrupt vector table contains jump instruction to
call ISR
Reset: 0x00
Undefined instruction: 0x04
Data Abort: 0x10
Interrupt: 0x18
0x100
Exception handler …
0x400
The interrupt handler …
0x00
Jump to reset handler …
0x04
Jump to interrupt
handler …
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32. Multiple Interrupts
ISR can be interrupted by another interrupt requests with a higher priority
Interrupt priorities should be set properly
Start
End
The 2nd ISR High Priority
Generate interrupt 1
Generate interrupt 2
The 1st ISR Low Priority
Start
End
Break
Resume
The main code
Break
Resume
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33. Multiple Interrupts (cont.)
If a low-priority interrupt comes while a high-priority interrupt is in process, the low-priority interrupt will be handled after the high- priority interrupt ISR finishes.
Start
End
The 2nd ISR High Priority
Generate interrupt 2
Generate interrupt 1
Start
End
The 1st ISR Low Priority
The main code
Break
Resume
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34. Development Environment
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35. Development Environment Cross Development: Host and Target Device
Architecture of development platform on a host differs from target device platform architecture
Different machine language is used
Development process
Coding
Compile
Download
Write to ROM,RAM, flash memory
Run and debug
Host
Target
Download
Software Development
Execution
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36. Development Environment C Toolchain
Object code
C code
Assembler
Linker
Assembly Code
Library
Executable code (Binary code)
Preprocessor
Compiler
C toolchain steps:
Preprocessor
Processes C code, handles “include”, pragma and macro expressions
Compiler
Transforms C language source code into assembly code
Assembler
Converts Assembly code into object code
Linker
Links one or more object code files with multiple libraries and generates executable code
Cross development: the same toolchain is used, but cross-compiler, cross-assembler, and cross-linker are used instead of common tools
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37. Development Environment GNU Toolchain Example
To build an application gcc is used
Preprocessor: cpp
Compiler: cc1
Assembler: as
Linker: ld
Example:
$gcc -v -Wl,-v a.c
Reading specs from /usr/lib/gcc/i686-pc-cygwin/3.4.4/specs ..
/usr/lib/gcc/i686-pc-cygwin/3.4.4/cc1.exe -quiet -v -D__CYGWIN32__
...
/usr/lib/gcc/i686-pc-cygwin/3.4.4/../../../../i686-pc-cygwin/bin/as.exe -o \
/cygdrive/c/DOCUME~1/honda/LOCALS~1/Temp/cc0KPUpz.o …
/usr/lib/gcc/i686-pc-cygwin/3.4.4/collect2.exe -Bdynamic …
/usr/lib/gcc/i686-pc-cygwin/3.4.4/../../../../i686-pc-cygwin/bin/ld.exe …
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38. Development Environment Cross-development Toolchain Example
The GNU compiler supports many processors for cross- development
ARM, SH, MIPS, PowerPC, AVR, V850
Toolchain
Similar to common toolchain
Example for ARM
$arm-none-eabi-gcc -v -Wl,-v a.c
gcc version (CodeSourcery ARM 2006q1-6) ..
c:/arm/sourceryg++/bin/../libexec/gcc/arm-none-eabi/4.1.0/cc1.exe -quiet
...
c:/arm/sourceryg++/bin/../lib/gcc/arm-none-eabi/4.1.0/../../../../arm-none-eabi/bin/as.exe … …
c:/arm/sourceryg++/bin/../libexec/gcc/arm-none-eabi/4.1.0/collect2.exe …
c:/arm/sourceryg++/bin/../lib/gcc/arm-none-eabi/4.1.0/../../../../arm-none-eabi/bin/ld.exe …
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39. Development Environment Integrated Development Environment
IDE (Integrated Development Environment)
All tools in one + GUI environment
Editor, compiler, debugger, project management, version control
Integrated Development Environment for PC
Eclipse – can be tuned up for using with dedicated platform
Visual Studio
CodeWarrior
Emacs – good for writing code and debugging
Remote development and debug – command line mode is more suitable than IDE
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40. Development Environment Cross-Compiler Specific
More target specific options:
Endian, float variables handling
Examples of target-dependent compilation options (gcc for Nios II):
Meb: use big-endian byte order
Mel: use little-endian byte order
Mno-hw-mul: disable MUL instructions
Mno-hw-div: disable DIV instructions
Msmallc: link with a limited version of the C std. library
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41. Development Environment Cross-Compiler: Optimization
Compiler options for speed and size optimization
Calculate some sub-expression on compilation time
Expand cycles
Power saving optimization achieved by correct design and deep research
Debug
Instructions can be out of order as a result of optimization, it is difficult to provide correspondence with source code during debug session
Modified variable value may not be accessible immediately
Compiler optimization may contain errors
Example:
SH4 processor, gcc cross-compiler
Function with a lot of if() … else checks with different return (0,1,2)
With optimization turned on, returned invalid extra large value
Solution: turn off optimization or rewrite code to use only 1 return at the end of the function
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42. Development Environment Cross-Compiler: Inline Assembler
Allows writing of assembly code directly in a C program
In C, some special processor instructions can be inaccessible
Operations with a control register
Interrupt enable/disable instructions
Is used to write optimized code
Examples of inline assembly:
Described by special function:
Described by pragma:
_asm(“ fset I”);
#pragma ASM
fset I
fclr I
#pragma ENDASM
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43. Development Environment Cross-Linker: Role of Linker
Multi-file program: each file is compiled individually into object files
The linker combines all object files and libraries to form the final executable
Linker operations
Symbol resolution
Relocation
module_a.c
Compiler
module_a.o
Linker
module_b.c
Compiler
module_b.o
abc_program
lib_c
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44. Development Environment Cross-Linker: Object File
Object file contains binary data that can be linked with other object files or executed
Common object file formats:
COFF - common object file format
ELF - executable and linking format
Common sections of an object file:
.text – program binary code
.rodata – read only data, strings in printf() for example
.data – initialized global variables
.bss – black storage start, not initialized global variables, does not take place in an object file
int foo(void)
{ … }
.text
int data_b = 4;
.data
.rodata
int data_c;
.bss
const int data_a = 1;
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45. Development Environment Cross-Linker: Symbol Resolution
C program example
main.c
extern int sum();
char array[] = {1, 4, 5, 19};
int main() {
int sum_val = 0;
sum_val = sum();
return sum_val; }
sum.c
extern char array[];
int sum() {
int i = 0;
int value = 0;
for (i = 0; i < ARRAY_SIZE, i++)
value += array[i]; }
return value;
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46. Development Environment Cross-Linker: Symbol Resolution (cont.)
Symbol types
Global symbols defined in a current module and used in other modules
All non-static functions and variables
Global symbols used in a current module but defined in other modules
External functions and variables
Local symbols defined and used in a current module
Static functions and variables
Compiler marks unresolved symbols, linker finds references in other files and patches code with correct value
Linker checks for multiple symbols definition
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47. Development Environment Cross-Linker: Symbol Resolution (cont.)
Static library is a set of several object files
gcc main.o sum.o /usr/lib/libc.a
During linking, linker checks object files from left to right as specified in the command line
Linker initializes 3 sets:
O – set of object files that will be linked to executable
U – set of unresolved symbols
D – set of resolved symbols
For each input object file linker performs:
Puts object file to set O
Updates set U and D
For each library file linker performs:
Checks object files in it, and if needed puts it into O
When all target files are processed, checks sets U and D
If U contains unresolved symbols, an error appears
If symbol is defined in several libraries, takes it from the 1st
Pay attention to libraries with cyclic dependences
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48. Development Environment Cross-Linker: Relocation
Relocation is the process of changing addresses already assigned to symbols to reflect the newly assigned address
Reason for symbol address change:
Section merging
Section placement
The sections with the same name from each file is placed contiguously
main.o
Memory
.text(main.c)
.text(main.c)
.text
.rodata(main.c)
.text(sum.c)
.data(main.c)
Cross-linker
.rodata(main.c)
.rodata
.rodata(sum.c)
sum.o
.text(sum.c)
.data(main.c)
.data
.rodata(sum.c)
.data(sum.c)
.data(sum.c)
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49. Development Environment Cross-Linker: Relocation (cont.)
Section placement
After compiling each section, is assumed to start from address 0 => symbol address values relative to start of the section
When the final executable is created, the section is placed at some address X => increment symbol address values
Start address of executable code can be assigned on linking time
Example:
Executable code of main() and sum() is placed together starting with 0x100
Start address of array[] moved, offset value = 0x100 + size of .text section
Patch symbol address values of sum() and array[]
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