1. A Case Study of the Rehosting from VHDL to Matlab/C
Presenter: Yulong Zou
Stevens Institute of Technology
Sep. 2, 2010 1

2. Outline Basic Structure of a VHDL Code
Challenging Issues and Solutions to the VHDL Rehosting
A Case Study of the VHDL Rehosting for an ADDER
Next Step 2

3. Basic Structure of a VHDL Code
In VHDL, a digital system consists of a design entity that can contain other entities that are then considered components by the top-level entity. Each entity is typically modeled by an entity declaration and an architecture, as shown below: 3

4. A General Entity Declaration Form
Entity Declaration (Interface): It defines the NAME of the entity and lists the input and output ports. The general form is shown as follows,
entity NAME_OF_ENTITY is
port (signal_names: mode type;
signal_names: mode type; :
signal_names: mode type);
end [NAME_OF_ENTITY] ; 4

5. A General Architecture Body Description
Architecture (Body): This specifies how a digit circuit operates and how it is implemented. A general form of an architecture body is described as,
architecture architecture_name of NAME_OF_ENTITY is
-- Declarations
-- components declarations, procedure declarations
begin
-- Statements :
end architecture_name; 5

6. Challenging Issues and Solutions
Abstraction of an Entity Declaration: In VHDL, an entity declaration typically defines the input and output ports.
Solution: use an input place and an output place to describe the semantics of an input and an output ports, respectively.
Abstraction of an Architecture Body: An architecture body generally specifies the detailed implementation of an entity.
Solution: a path is used to describe the semantics of an architecture. 6

7. Other Issues Related to VHDL Abstraction
Many Other Unique Keywords: Differing from C/C++/ Matlab, VHDL has many other unique keywords, e.g., signal, process, in, out, downto, file, exit, and so on.
Solution: For a signal and a process declarations, we use a place and a path to describe the corresponding semantics . 7

8. A Case Study of VHDL Code for an ADDER
The entity declaration of an ADDER:
entity ADDER is
port(A: in std_logic_vector(1 downto 0);
B: in std_logic_vector(1 downto 0);
sum: out std_logic_vector(2 downto 0) );
end ADDER; 8

9. Graphic Representation of Entity Declaration
Input Ports (A and B): Output Port (sum): 9

10. Architecture of an ADDER
The architecture body:
architecture behv of ADDER is
-- define a temporary signal to store the result
signal result: std_logic_vector(2 downto 0);
begin
-- the 3rd bit should be carry
result <= ('0'&A)+('0'&B);
sum(2 downto 0) <= result(2 downto 0);
end behv; 10

11. Graphic Representation of Architecture
The following shows a graphic representation of the entity body: 11

12. Rehosting of the VHDL-ADDER to C/Matlab12

13. Next Step
To extend XML representation capabilities to handle other VHDL keywords, such as, group, file, exit, and so on.
To complete the inference engine, e.g., to enable the rehosting from VHDL to C++. 13

14. Q&A 14