1. COMPUTER ARCHITECTURE (PoCA)
EKT303/4
PRINCIPLES OF
COMPUTER ARCHITECTURE (PoCA)

2. Staffs Fazrul Faiz Zakaria Rafikha Aliana A.Raof Phaklen Ehkan
Rafikha Aliana A.Raof
Phaklen Ehkan
Mohammad Nazri Md. Noor

3. Textbook

4. ------- refer teaching plan--------
Contents (lecture)
Chap. 1: Introduction to Comp. Architecture
Chap. 2: Foundation to Comp. Architecture
Chap. 3: Design Methodology
Chap. 4: Central Processing Unit (CPU) Basics
Chap. 5: Processor Internals
Chap. 6: Enhancing CPU Performance
Chap. 7: CPU Externals
Chap. 8: Practical Embedded CPUs
Chap. 9: Evolution of Computer Architecture
refer teaching plan

5. Laboratory VHDL as hardware programming
Altera Quartus II as a development platform
Altera DE FPGA board

6. Optimised Netlist (Gate level)
VHDL – Design Flow
VHDL entry
compilation
Netlist (Gate level)
optimization
synthesis
Optimised Netlist (Gate level)
simulation
Place & route
Physical device
simulation

7. Code Structure – Fundamental VHDL units
Library declaration
Basic VHDL Code
Entity
Architecture

8. Example VHDL code for FA unit
library ieee; use ieee.std_logic_1164.all; entity full_adder is port (a,b,cin : in bit; s, cout : out bit; end full_adder; architecture dataflow of full_adder is begin s <= a XOR b XOR cin; cout <= (a AND b) OR (a AND cin) OR (b AND cin); END dataflow;
circuit

9. Contact Hours Lecture: Laboratory:
Wednesday: (CompE), (CommE), (CompNetE)
Thursday: (CompE), (CommE), (CompNetE)
Laboratory:
Tuesday: (CompE), (CommE), (CompNetE)

10. Test, Quiz & Assignment = 30% Lab. Component = 20% Final Exam = 50%
Assessment
Test, Quiz & Assignment = 30% Lab. Component = 20% Final Exam = 50%

11. End of Intro..