1. EGR 2131 Unit 7 Sequential Logic: Analysis
Read Mano & Ciletti, Sections 5.1 to 5.5.
Homework #7 and Lab #7 due next week.
Quiz next week.
-Handouts: Unit 7 practice sheet.

2. Rview: Useful Building-Block Circuits
Here are some kinds of digital circuits we’ve studied or will study in the weeks ahead:
Adders
Comparators
Decoders
Encoders Chapter Combinational
Code converters
Multiplexers
Latches & Flip-flops Chapter 5
Shift registers Chapter 6
Counters Sequential
Memory Chapter 7

3. Review: Combinational Versus Sequential
A combinational logic circuit is a circuit whose output depends only on the circuit’s present inputs. (“Has no memory of the past.”)
Covered in the book’s Chapter 4.
A sequential logic circuit is a circuit whose output may depend on the circuit’s previous states as well as its present inputs. (“Has a memory.”)
Covered in the book’s Chapter 5.
Examples: Bell that rings if key in ignition and door open.
Microwave panel that remembers keys pressed before START. 3

4. Review: Feedback Paths
The key to creating sequential circuits (ones that “have memory”) is to include feedback paths, which route the output from a gate back to the input of an earlier gate.
Example of a circuit with a feedback path: 4

5. Review: Components with Internal Feedback Paths
We’ll see in Chapter 5 that components called latches and flip-flops have internal feedback paths. Here are logic symbols for some latches and flip-flops:
Each of these boxes contains several interconnected gates with feedback paths. 5

6. Review: How To Tell Whether a Circuit Is Combinational Or Sequential
A circuit is sequential if its logic diagram contains feedback paths or contains sequential components such as latches or flip-flops.
Otherwise it is combinational. So if the diagram just contains gates, and does not have any feedback paths, then the circuit is combinational. 6

7. Five Latches and Flip-flops
Our textbook discusses about five kinds of latches and flip-flops (more if you count variations such as optional inputs and whether the inputs are active-high or active-low):
SR latch
D latch
D flip-flop
JK flip-flop
T flip-flop
-Draw symbols of all 5 latches and flip-flops. (Many also available with active-low inputs).
The most important in modern circuits. 7

8. A One-Bit Memory
Every latch and flip-flop is a memory device that can store a single bit—i.e., either a single 1 or a single 0.
They differ from each other in terms of how you store the value in it.
The value being stored is available on an output pin named Q.
In many cases an inverted output, named Q′, or QN, or 𝑄 , is also available. 8

9. Some Latch and Flip-Flop Symbols
In all of these, inputs are on the left, top, and bottom, and outputs are on the right.
From the book:
From Quartus II:
Input with triangle means it’s a flip-flop, not a latch.
Book’s symbols show both normal output and inverted output. Quartus shows only normal output. 9

10. Choices in Quartus II
In Quartus II you have your choice of generic latches and flip-flops, or latches and flip-flops having the same features as the ones in 74XX-series chips.
To use the latter, you must know the 74XX number for the chip you want. Some examples are listed here.
Recall that Wikipedia has a complete list of 74XX chips (not all of which are available in Quartus.)
Type
Sample Chips
S-R latch
74279
D latch
7475
D flip-flop
7474
J-K flip-flop
7476
-Draw symbols of all 5 latches and flip-flops. (Many also available with active-low inputs). 10

11. Choices in Quartus II (Cont’d.)
Generic:
74XX:
A 7474 chip contains two D flip-flops, each of which has its own inputs named D, CLK, PRN, CLRN, and its own outputs named Q and QN. 11

12. Choices in Quartus II (Cont’d.)
The choices on the previous slide assumed that you’re using schematic entry to draw a diagram of your design.
Another alternative is to use text entry with VHDL. Later we’ll see examples of VHDL code that get synthesized into latches and flip-flops. 12

13. Terminology: “Set” and “Reset”
When discussing latches and flip-flops, we often use the terms set and reset.
To set a latch or flip-flop means to put it in a state where its 𝑄 output is 1. (And its 𝑄 output, if it has one, is 0.)
To reset a latch or flip-flop means to put it in a state where its 𝑄 output is 0. (And its 𝑄 output, if it has one, is 1.) 13

14. Latches
A latch is a temporary storage device that has two stable states (bistable). It is a basic form of memory that stores a single bit.
The SR (Set-Reset) latch is the most basic type. It can be built from NOR gates or NAND gates. With NOR gates, the latch responds to active-HIGH inputs. R Q
1st type of latch: S-R latch.
Do practice questions 1 – 5. Q′ S
SR Latch with NOR gates

15. SR Latch
The SR latch is in a stable (latched) condition when both inputs are LOW. R S Q Q′ 1
Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (0). To SET the latch (Q = 1), a momentary HIGH signal is applied to the S input while the R remains LOW.
Latch initially RESET 1 R S Q Q′ 1
To RESET the latch (Q = 0), a momentary HIGH signal is applied to the R input while the S remains LOW.
Latch initially SET 1

16. Function Table for SR Latch (active-high inputs)Q Q′
Comments Q0
Q0′
No change. 1
RESET
SET
Invalid state
-Do Practice Question 6.
To avoid the invalid state, designers using this latch in a circuit must ensure that S and R can never be high at the same time. 16

17. Function Table for SR Latch (active-low inputs)
Some SR latches (built with NAND gates instead of NOR gates) have active-low inputs: S R Q Q′
Comments 1 Q0
Q0′
No change.
RESET
SET
Invalid state 17

18. Function Table for SR Latch with Control Input (active-high inputs)En S R Q Q′
Comments X Q0
Q0′
No change 1
RESET
SET
Invalid state
-Again, this assumes S and R active-high; another kind has S and R active-low. 18

19. Example Solution SR Latch with Control Input
This variation on the basic SR latch has an additional input called enable (En) that must be HIGH in order for the latch to respond to the S and R inputs.
Example
Show the Q output with relation to the input signals. Assume Q starts LOW.
Solution
Keep in mind that S and R have effect only when En is HIGH.
-Do as Practice Question 7. S R En Q

20. A simple rule for the D latch is:
The D latch is similar to the SR latch with control input but combines the S and R inputs into a single D input as shown: Q Q′
-2nd type of latch: D Latch.
A simple rule for the D latch is:
Q follows D when the Enable is active.

21. D Latch
The function table for the D latch summarizes its operation. If En is LOW, then there is no change in the output and it is latched.

22. Q
D Latch
Example Q′
Determine the Q output for the gated D latch, given the inputs shown.
-Do as Practice Question 8.
Notice that the Enable is not active during these times, so the output is latched.

23. Two Popular Latch Chips
74279 (Quad active-low SR latch)
7475 (Quad D latch) 23

24. Level-Triggered versus Edge-Triggered
SR latches and D latches are often called level-triggered devices, because the output can change any time the enable input is at the correct level.
Other devices, such as flip-flops, are edge-triggered, because the output can only change when there is a rising or falling edge on the clock input. 24

25. Master Clock in a System
Many digital systems have a master clock signal that drives and synchronizes everything in the system.
This signal is a high-frequency square wave.
If I say that the new computer I bought has a 1 GHz clock, I’m talking about the frequency of this master clock. 25

26. The active edge can be positive or negative.
Flip-flops
A flip-flop differs from a latch in the manner it changes states. A flip-flop is a clocked device, in which only the clock edge determines when a new bit is entered.
The active edge can be positive or negative.
Dynamic input indicator
Rising edge-triggered
Leading edge-triggered
Falling edge-triggered
Trailing edge-triggered

27. D Flip-flops
The truth table for a positive-edge triggered D flip-flop shows an up arrow to remind you that it is sensitive to its D input only on the rising edge of the clock; otherwise it is latched. The truth table for a negative-edge triggered D flip-flop is identical except for the direction of the arrow.
-1st type of flip-flop: D flip-flop
-Do Practice Questions 9 & 10.
(a) Positive-edge triggered (b) Negative-edge triggered

28. JK Flip-flops
The J-K flip-flop is more versatile than the D flip flop. In addition to the clock input, it has two inputs, labeled J and K. When both J and K = 1, the output changes states (toggles) on the active clock edge (in this case, the rising edge).
-2nd type of flip-flop: J-K flip-flop.

29. Example Solution JK Flip-flopsQ J
Example
CLK
Determine the Q output for the J-K flip-flop, assuming Q is initially high. Q K
Notice that the outputs change on the rising edge of the clock.
Solution
Set
Toggle
Set
Latch
CLK
-Do Practice Question 11. J K Q

30. Synchronous versus Asynchronous Inputs on Flip-flops
Synchronous inputs (for example the D or J-K inputs) affect the output on the triggering edge of the clock. Many flip-flops also have other inputs that are asynchronous, meaning they affect the output independent of the clock.
PRE
Two such inputs are normally labeled PRE (preset) and CLR (clear). These inputs are usually active LOW, as shown here.
Other common names for these pins are SET and RESET. Q J
-Up to now we’ve only been considering the synchronous inputs.
-Note that this involves adding a couple more inputs to the symbol I drew earlier for a J-K flip-flop.
-Sometimes the async inputs have different labels (such as ~SET and ~RESET, or ~S and ~R).
CLK Q K
CLR

31. Example Solution Flip-flops Flip-flops
PRE
Flip-flops
Flip-flops Q J
Example
CLK
Determine the Q output for the J-K flip-flop, assuming Q is initially high. K Q
Solution
CLR
Set
Toggle
Set
Reset
Toggle
Latch
CLK J
-Do Practice Question 12. K
Set
PRE
Reset
CLR Q

32. Two Popular Flip-Flop Chips
7474 (Dual D Flip-Flop)
74LS76 (Dual J-K Flip-Flop) 32

33. Flip-flop Timing Characteristics
Propagation delay time is specified for the rising and falling outputs. It is measured between the 50% level of the clock to the 50% level of the output transition.
50% point on triggering edge
CLK
CLK
50% point
50% point on HIGH-to- LOW transition of Q
The material on this slide and on the next three slides is discussed in Chapter 11, which we’ll skip due to time constraints. Q
50% point on LOW-to-HIGH transition of Q Q
tPLH
tPHL
The typical propagation delay time for the 74AHC family (CMOS) is 4 ns.

34. Flip-flop Timing Characteristics
Another propagation delay time specification is the time required for an asynchronous input to cause a change in the output. Again it is measured from the 50% levels. The 74AHC family has specified delay times under 5 ns.
50% point
CLR
50% point
PRE Q
50% point Q
50% point
tPHL
tPLH

35. Flip-flop Timing Characteristics
Set-up time and hold time are times required before and after the clock transition that data must be present to be reliably clocked into the flip-flop.
Setup time is the minimum time that the data must be present before the clock. D
CLK
Set-up time, ts
Hold time is the minimum time that the data must remain after the clock. D
CLK
Hold time, tH

36. Flip-flop Timing Characteristics
Other timing specifications include maximum clock frequency and minimum pulse widths for various inputs.
Consult the following datasheet to compare propagation delays, set-up time, hold time, and maximum clock frequency for a 7474, a 74LS74, and a 74S74:
7474 datasheet
-Do Practice Question 13.

37. Summary of Flip-Flop Behavior
The following characteristic tables summarize the operation of our three kinds of flip-flops.
You should memorize these, just as you’ve memorized the truth tables of the basic gates. 37

38. Summary of Flip-Flop Behavior (Cont’d.)
Characteristic equations are another way of summarizing flip-flop behavior. They contain the same info as characteristic tables, but in the form of Boolean equations.
For D flip-flop, Q(t+1) = D.
For JK flip-flop, Q(t+1) = JQ′ + K′Q.
For T flip-flop, Q(t+1) = TQ′ + T′Q = T  Q.
Don’t confuse the two uses of + here: Q(t+1) means the next value of Q, but JQ′+K′Q means JQ′or K′Q. 38

39. Sequential Circuits: Analysis
Now that we know how individual flip-flops behave, we’ll look at clocked sequential circuits that contain gates and flip-flops that are all clocked by the same clock signal.
Another name for this kind of circuit is synchronous sequential circuits.
From now on we’ll just call these sequential circuits. In this course we won’t consider other possibilities, such as circuits whose flip-flops have different clock signals. 39

40. Review: Analysis of Combinational Circuits
Recall that with a combinational circuit such as the one shown, the inputs determine the outputs. So if you know the present input values, you can figure out the present output values. 40

41. Sequential Circuits: Analysis
With a sequential circuit, knowing the present input values is not enough to let you figure out the present output values. You also need to know the values stored in each of the circuit’s flip-flops.
We call the collective values of the flip-flops the circuit’s state. 41

42. Sequential Circuits: Example
Suppose that in this circuit, you know that x = 0. Can you figure out the values of A, B, and y?
No, not unless you also know the circuit’s state (i.e., the values stored in the two flip-flops). 42

43. Sequential Circuits: Example (Cont’d.)
This circuit contains two D flip-flops with outputs named A and B.
These flip-flop outputs are also outputs from the circuit as a whole.
This is not always the case. In some circuits the flip-flop outputs are used internally but are not brought out as circuit outputs.
Either way, the circuit’s state is the combined values stored in all the flip-flops.
Example: In the circuit shown, if flip-flop A holds a 1 and flip-flop B holds a 0, we say that we’re in state 10. 43

44. State Tables
Recall that when analyzing a combinational circuit we build a truth table, which lists the output values for every possible combination of input values.
When analyzing a sequential circuit we build a state table, which lists the output values and the next state for every possible combination of input values and the present state. 44

45. State Table: Example
Highlighted line says that if flip-flop A holds a 0 and flip-flop B holds a 1 and input x = 0, then:
the output y = 1 (right now)
flip-flops A and B will both hold 0 after the next clock pulse.
Do Practice Question. 45

46. State Table: Example (Cont’d.)
For a state table to be complete, it must list all possible combinations of present state and input.
In this example the first three columns list all combinations from 000 to 111, just like a truth table with three inputs.
Do Practice Question. 46

47. State Table: Another Form
Here’s another way of drawing the same state table from the previous slide. Note that instead of listing the input x in a column next to the present state, each possible value of x gets its own columns.
Do Practice Question. 47

48. State Diagram
A state diagram holds the same info as a state table but presents it in more graphical form.
Each possible state is represented by a node (or circle) with the flip-flop values written inside it.
Each possible state transition is represented by an arrow with a label that tells which input value results in this transition, along with the corresponding output value (right now). 48

49. State Diagram: Example
The state diagram shown below matches the state table shown previously.
Do Practice Question.
This arrow says that if flip-flop A holds a 0 and flip-flop B holds a 1 and input x = 1, then:
the output y = 0 (right now)
flip-flops A and B will both hold 1 after the next clock pulse. 49

50. Sequential Circuit Analysis
Analysis of a sequential circuit typically starts with a logic diagram and ends with a state table or state diagram, and, possibly, a description in English of the circuit’s behavior (such as “This circuit is a four-bit up-counter: its output increases by 1 on each clock pulse from to 11112, and then starts over again at ”) 50

51. Sequential Circuit Analysis: Example
Suppose we know the present state is 00 and the input x=0. Can we figure out the value of y and the next state? Yes! 1 1
Do Practice Question 1 51

52. Sequential Circuit Analysis: Another Example
Build the state table and state diagram for the circuit shown below. (Note that the flip-flop is drawn “backwards,” with inputs on the right and output on the left.)
If you don’t remember how a full adder works, here is its truth table:
Do as Practice Question 52

53. Algebraic Description of a Sequential Circuit
Instead of drawing a logic diagram, we can describe a sequential circuit algebraically (i.e., using Boolean equations.)
For this circuit, we have:
A(t+1) = Ax + xB
B(t+1) = A′x
y = (A + B)x′
Don’t confuse the two uses of + here: A(t+1) means the next value of A, but A+B means A or B.
Do Practice Question 53

54. Finite State Machines
Recall that the circuits we’ve been analyzing are called synchronous sequential circuits.
A fancier name is finite state machine (FSM).
FSMs are often further categorized as either Mealy machines or Moore machines. The difference depends on whether the outputs depend on the present state only, or on the present state and the inputs. (See next slide….) 54

55. Mealy Machines and Moore Machines
The only difference is whether outputs depend on inputs. 55

56. Analysis with JK or T Flip-Flops
The previous examples have used D flip-flops.
Analysis of circuits containing JK or T flip-flops is similar but slightly more work because these flip-flops’ outputs depend on their inputs in a more complex way. Recall: 56

57. Analysis with JK or T Flip-Flops: Example
Note that this circuit has no outputs other than the state itself, so it’s a .
Do as Practice Question
Build the state table and state diagram for the circuit above, recalling that JK flip-flops work like this: 57