1. GBT-FPGA 120 MHz Modification Status
Erno DAVID Wigner Research Center for Physics (HU)
6 April, 2016 1 1

2. GBT-FPGA Internal Block Diagram2 2 2

3. Simulation Results TX Modification:
Acknowledge signal – High value signals when the scrambler accepted the GBT payload, active for one clock cycle
RX Modification:
Valid signal – High value signals when the descrambler produced a new GBT payload 3 3 3

4. PCIe40 Transceiver Layout
MP[3]
MP[2]
PCIe[1]
MP[1]
PCIe[0]
MP[0]
TTC 4 4 4

5. P&R Result: 48 x TX (GBT Mode) + 48 x RX (GBT Mode)
Slow 900mV 100C Model Fmax Summary:
TX Clock Domains:
212 – 382 MHz
RX Clock Domains:
91 – 100 MHz
Fitter Status : (01:01:45 build time)
Quartus Prime Version : Build 189 Standard Edition
Family : Arria 10
Device : 10AX115S4F45I3SGE2
Timing Models : Preliminary
Logic utilization (in ALMs) : 43,203 / 427,200 ( 10 % )
Total registers : 38075
Total pins : 209 / 960 ( 22 % )
Total block memory bits : 0 / 55,562,240 ( 0 % )
Total RAM Blocks : 0 / 2,713 ( 0 % )
Total DSP Blocks : 0 / 1,518 ( 0 % )
Total HSSI RX channels : 48 / 72 ( 67 % )
Total HSSI TX channels : 48 / 72 ( 67 % )
Total PLLs : 56 / 152 ( 37 % ) 5 5 5

6. P&R Result: 48 x TX (GBT Mode) + 48 x RX (Wide Bus Mode)
Slow 900mV 100C Model Fmax Summary:
TX Clock Domains:
183 – 357 MHz
RX Clock Domains:
132 – 254 MHz
Fitter Status : (00:57:36 build time)
Quartus Prime Version : Build 189 Standard Edition
Family : Arria 10
Device : 10AX115S4F45I3SGE2
Timing Models : Preliminary
Logic utilization (in ALMs) : 20,835 / 427,200 ( 5 % )
Total registers : 33327
Total pins : 209 / 960 ( 22 % )
Total block memory bits : 0 / 55,562,240 ( 0 % )
Total RAM Blocks : 0 / 2,713 ( 0 % )
Total DSP Blocks : 0 / 1,518 ( 0 % )
Total HSSI RX channels : 48 / 72 ( 67 % )
Total HSSI TX channels : 48 / 72 ( 67 % )
Total PLLs : 56 / 152 ( 37 % ) 6 6 6