1. Digital Design: Sequential Logic Blocks
Credits:
Slides adapted from:
J.F. Wakerly, Digital Design, 4/e, Prentice Hall, 2006
C.H. Roth, Fundamentals of Logic Design, 5/e, Thomson, 2004
R.H. Katz, G. Borriello, Contemporary Logic Design, 2/e, Prentice-Hall, 2005

2. Registers A collection of 2 or more D flip flops with a common clock
Registers are often used to store a collection of related bits (e.g. a byte of data in a computer)
Clr D Q
OUT1
OUT2
OUT3
CLK
IN1
IN2
IN3
IN4
Clear
OUT4

3. A “standard” 4-bit register IC

4. A “standard” 8-bit register IC

5. Registers with 3-state outputs
(a) Symbol
(b) Functional Diagram

6. A “standard” 8-bit register with 3-state outputs

7. Registers with clock enable
D Q CK 1
In0 CE
ClrN
In7
Clk
In1
Out0
Out1
Out7 8 Q D CE
Load
Clk In
Out
Clr
ClrN
(a) Symbol

8. A standard 8 bit register with clock enable (= “gated” clock)

9. Registers application: Data Transfers

10. Shift Registers
It is a register that stores input values in sequence. At each clock tick the values stored are shifted from one flip flop to the adjacent
block diagram

11. Cascading Flip Flops tFF1 < Tclock – Tsu2 + tskew Setup Constraint:
Hold Constraint:
tFF1 > Th2 + tskew
If flip flops were ideal (tFF = 0) shift registers would not work ! The hold time constraint would not be satisfied !!
For long shift registers, skew can easily become an issue and cause hold time constraint to be violated

12. Shift Registers (cont’d)

13. Shift Registers (cont’d)

14. Shift registers (cont’d)

15. Universal shift register
serial or parallel inputs
serial or parallel outputs
permits shift left or right
shift in new values from left or right
clear sets the register contents and output to 0 s1 and s0 determine the shift function s0 s1 function hold state shift right shift left load new input
clear
output
input s0 s1
clock
Universal
Shift Register
right_out
left_in
left_out
right_in

16. Shift register application
Parallel-to-serial conversion for serial transmission
parallel outputs
parallel inputs
Parallel-to-serial conversion
Serial-to-parallel conversion
serial transmission

17. Shift register application (cont’d)
Pattern Recognizer
in this case, recognizing the pattern 1001 D Q IN
OUT1
OUT2
OUT3
OUT4
OUT
CLR
CLK

18. Shift register application (cont’d)
Ring Counter
counters are systems that sequences through a fixed set of patterns
in this case the sequence is 1000, 0100, 0010, 0001 provided that one of the given patterns is forced as initial state (by loading or set/reset)
NOTE: with 4 FF we
make only 4 patterns D Q IN
OUT1
OUT2
OUT3
OUT4
CLK
START S R

19. Shift register application (cont’d)
Johnson (= Moebius = Twisted-ring) Counter D Q IN
OUT1
OUT2
OUT3
OUT4
CLK
How does this counter work?
Counts through the sequence: , 1100, 1110, 1111, 0111, 0011, 0001, 0000
NOTE: with 4 FF we make 8 patterns. Adjacent patterns have
distance one (glitch free decoding)
we can use 0000 or
1111 as reset state

20. Ring and Johnson counter Timings

21. Binary Counters
A counter is a clocked sequential circuit that sequences through a fixed set of patterns
A counter with m-states is called a modulo-m-counter, or sometimes a divide-by-m counter
The most commonly used counter type is an n-bit binary counter (each of the states is encoded as the corresponding n-bit binary integer)

22. Binary Counters (cont’d)
Ripple counters
Don’t use them !!! The output of the flip-flops are fed into the clock pin causing skew. As a result reliability becomes an issue (especially for high speed applications).
Synchronous counters
The operation of the flip flops is synchronized by a common clock.

23. Synchronous Binary Counters

24. Synchronous Binary Counters (cont’d)

25. Sync. Binary Counters with T-FF
QA toggles always (every clock tick)
QB toggles every time QA = 1
QC toggles every time QA AND QB are both 1

26. Sync. Binary Counters with D-FF
XOR decides when bit should be toggled
The toggling rule is as follows: always for low-order bit; only when first bit is true for second bit; only when first and second bit are true for third bit; and so on D Q
OUT1
OUT2
OUT3
OUT4
CLK
"1"

27. Example: Binary Up/Down Counter

28. Binary Up/Down Counter (cont’d)