1. Adapted from Krste Asanovic
Verilog Tutorial
Adapted from Krste Asanovic

2. Verilog Fundamentals History Data types Structural Verilog
Functional Verilog

3. Originally designers used manual translation + bread boards for verification

4. Hardware design languages enabled logic level simulation and verification

5. Once design were written in HDLs tools could be used for automatic translation

6. Primary Verilog data type is a bit-vector where bits can take on one of four values

7. The Verilog keyword wire is used to denote a standard hardware net

8. Verilog includes ways to specify bit literals in various bases

9. Verilog Basics
Data types
Structural Verilog
Functional Verilog

10. A Verilog module includes a module name and a port list

11. A Verilog module includes a module name and a port list

12. A module can instantiate other modules creating a module hierarchy

13. A module can instantiate other modules creating a module hierarchy

14. A module can instantiate other modules creating a module hierarchy

15. Verilog supports connecting ports by position and by name

16. Let’s review how to turn our schematic diagram into structural Verilog

17. Let’s review how to turn our schematic diagram into structural Verilog

18. Verilog Fundamentals Data types Structural Verilog Functional Verilog
Gate level
Register transfer level
High-level behavioral

19. Functional Verilog can roughly be divided into three abstraction levels

20. Gate-level Verilog uses structural Verilog to connect primitive gates

21. Continuous assignments statements assign one net to another or to a literal

22. Using continuous assignments to implement an RTL four input mutliplexer

23. Verilog RTL includes many operators in addition to basic boolean logic

24. Verilog RTL operators

25. Always blocks have parallel inter-block and sequential intra-block sematics

26. Always blocks have parallel inter-block and sequential intra-block sematics

27. Always blocks have parallel inter-block and sequential intra-block sematics

28. Always blocks have parallel inter-block and sequential intra-block sematics

29. Always blocks have parallel inter-block and sequential intra-block sematics

30. Continuous and procedural assignment statements are very different

31. Always blocks can contain more advanced control constructs

32. What happens if the case statement is not complete?

33. What happens if the case statement is not complete?

34. So is this how we make latches and flip-flops?

35. To understand why we need to know more about Verilog execution semantics

36. To understand why we need to know more about Verilog execution semantics

37. To understand why we need to know more about Verilog execution semantics

38. To understand why we need to know more about Verilog execution sematics

39. To understand why we need to know more about Verilog execution sematics

40. To understand why we need to know more about Verilog execution semantics

41. To understand why we need to know more about Verilog execution semantics

42. To understand why we need to know more about Verilog execution sematics

43. To understand why we need to know more about Verilog execution sematics

44. We didn’t model what we expected due to Verilog execution semantics

45. Non-blocking procedural assignments add an extra event queue

46. Non-blocking procedural assignments add an extra event queue

47. The order of non-blocking assignments does not matter

48. Common patterns for latch and flip-flop inference

49. Writing Good Synthesizable Verilog

50. Behavioral Verilog is used to model the abstract function of a hardware

51. Verilog can be used to model the high-level behavior of a hardware block

52. Delay statements should only be used in test harnesses

53. System tasks are used for test harnesses and simulation management

54. Which abstraction is the right one?

55. Examples

56. Mux4: Gate-level structural Verilog

57. Mux4: Using continuous assignments

58. Mux4: Behavioral style

59. Mux4: Using always block

60. Mux4: Always block permit more advanced sequential idioms

61. Parametrized mux4

62. Flip-flops

63. Flip-flops with reset

64. Register

65. Register in terms of Flip-flops

66. Static Elaboration: Generate

67. A simple state machine for valid/ready signals

68. Implementing the control logic finite state machine in Verilog

69. Implementing the control signal outputs for the finite state machine

70. Implementing the state transitions for the finite state machine

71. Take away points