1. Modeling of Failure Probability and Statistical Design of Spin-Torque Transfer MRAM (STT MRAM) Array for Yield Enhancement
Jing Li, Charles Augustine, Sayeef Salahuddin
and Kaushik Roy
School of Electrical and Computer Engineering,
Purdue University

2. MRAM combines all desired memory attributes
Why MRAM?
Metrics
SRAM
DRAM
MRAM
Read speed
Fast
Moderate
Write speed
Non-Volatile No
Yes
Refresh
Cell size
Large
Small
Low Voltage
MRAM combines all desired memory attributes

3. Conventional MRAM vs. STT MRAM
Bit line
Bit line
Drive Transistor
MTJ
Free layer
Isolated Transistor
Free layer
MTJ
Fixed layer
Fixed layer
Digital line
Word line
Word line
Source line
Programmed by external magnetic field
High write current
Poor scalability
Programmed by internal spin-polarized current
Low write current
Good scalability

4. Outline Basic operating principle
Design challenges: process variations
Fault modeling for read and write operation
Robust cell design: cell level optimization
Statistical design considering cell and memory architecture
Conclusion

5. Anti-parallel configuration Parallel configuration
Basics of STT MRAM
3D structure : 1T1M cell
Free layer
High R (“1”) S
Substrate
Bit line
Gate Oxide
Word line
Source line
Tunneling Oxide
Fixed layer
Anti-parallel configuration
Free layer D
Tunneling Oxide
Low R (“0”)
Fixed layer
Parallel configuration
Magnetic Tunneling Junction (MTJ) can be configured as
High resistance state (anti-parallel, “1”)
Low resistance state (parallel, “0”)
Programmed by internal spin-polarized current
Low write current
Good scalability

6. Operating Principle Static high/low R depends on-1
-0.5
0.5 1
1.5 2
2.5
Applied voltage (V)
MTJ Resistance (normalized) R AP P I
> HL LH BL
Write “1”
RMTJ WL
Write “0” SL
Static high/low R depends on
Voltage
Cross sectional area/oxide thickness
Dynamic switching threshold current (ITH)depends on
Operating frequency
Cross sectional area

7. What is the major challenge in STT MRAM?

8. Process Variation In MTJ
Variation in A
R exp( )
R exp( ) t
R /A
MTJ
Free layer t
Fixed layer A
Static R
Sources of variations
Oxide thickness (t)
Exponential dependency of high/low resistance
Cross sectional area (A)
Static resistance: R α1/A
Dynamic switching threshold: ITH (~A x JTH)α A
Dynamic ITH
-ITH(f,A)
+ITH(f,A)

9. Process Variation In MTJ
Frequency dependency*
Static R
MTJ
Free layer
Fixed layer t A
Dynamic ITH
-ITH(f,A)
+ITH(f,A)
Dynamic switching threshold current density (JTH)
Determined by material properties
Varies with operating frequency
*Hosomi et al., A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-RAM, IEDM Tech. Dig., pp , Dec., 2006.

10. How to Estimate Parametric Failures at Early Design Phase?

11. Read Operation
Failure!!
Wrong decision
Failure!!
0-1 disturbance
-ITH
+ITH Rp
RAP
IREF
Bit line Δ IP Δ
IAP
direction reading
Anti-parallel
RAP or RP
Word Line
Parallel direction
reading
Source line
Read operation : parallel (P) or anti-parallel (AP) direction reading
Read failure
wrong decision (Sense Amp.)
Cell storing “0”=> read out as “1”
Cell storing “1”=> read out as “0”
read disturbance
Cell flips => “1-to-0” disturbance (P)or “0-to-1” disturbance (AP)

12. Read failure Two operation modes Parallel direction reading
High current  read disturbance
Anti-parallel direction reading
Low current  wrong decision

13. Read failure Design parameter impact on read failure probability t
NMOS sizing: insensitive
Operating frequency: insensitive
Sensitivity to parameter variation: dominate t

14. Write Operation Bi-directional write operation
RAP
Write “1” R
MTJ
Write Margin
Write Margin RP
Write “0”
-ITH(f,A)
+ITH(f,A)
Bi-directional write operation
Unsuccessful write due to
Write current less than switching threshold current

15. Write Failure Unbalanced writing strength
MTJ
Write “0”
RAP
Unbalanced writing strength
Write “0”(strong) vs. Write “1” (weak)
Design parameter impact on PWF
NMOS sizing
Operating frequency RP
-ITH(f,A)
+ITH(f,A)

16. Statistical Design Methodology
PMEM No
Cell optimization PF
Cell: Estimation of failure probability
Memory architecture and design parameters
Yield maximum?
Yes
Structural and Electrical
Specs for Memory
(NRow, NCOL,NRC fW, fR, AMEM
Redundant Columns NRC PF
PCOL
Statistical design methodology
Cell optimization
Architecture optimization

17. Cell Optimization Cell failure probability can be minimized by
Optimal Operation Region
Cell failure probability can be minimized by
Optimal design read drive circuitry
Optimal sizing NMOS transistor
PF=PRF+PWF-PRFPWF ≈0

18. Memory architecture
PMEM
Redundant Columns NRC PF
PCOL
Optimal memory configuration under process variation
Under area constraint
Yield enhancement

19. Conclusions
Parametric failures in STT MRAM depends on process variations.
Estimation of failures is required at the design phase.
CAD framework is developed to simulate spintronics-based circuits
Statistical design methodology effectively improves yield.
Analysis and reduction of parametric failures in STT MRAM is essential to yield enhancement.

20. Thank You!
Acknowledgements
C2S2 FCRP and NRI