1. Valerio Re INFN Pavia and University of Bergamo
Summary of the SVT parallel sessions
Valerio Re
INFN Pavia and University of Bergamo
SuperB Workshop and Kick-Off Meeting
Elba, May 29 – June 2, 2011
V. Re
SuperB Workshop and Kick-Off Meeting - Elba, June 1, 2011

2. SuperB Workshop and Kick-Off Meeting - Elba, May 31, 2011
40 cm
30 cm
20 cm
Layer0
old beam pipe
new beam pipe
SVT (I)
SVT Baseline for TDR
Striplets in R~1.5 cm
5 layers of silicon strip modules (extended coverage w.r.t BaBar)
Upgrade Layer0 to thin pixel for full luminosity run
more robust against background occupancy
Several progress on the baseline design in the last few months:
Definition of the requirements for readout chips for striplets and strip:
Need to develop 2 new chips since existent chips do not match all the requirements : analog info, very high rates in inner Layers (0-3) & short shaping time, long shaping in Layers 4-5 to reduce noise for long modules.
Started to evaluate if readout architecture for pixels can be used for strips as well: no evident showstopper up to now, but manpower is critical and contribution from new groups is welcome!
First estimate of noise vs shaping time in each layer done: some optimization still needed.
SuperB Workshop and Kick-Off Meeting - Elba, May 31, 2011

3. SuperB Workshop and Kick-Off Meeting - Elba, May 31, 2011
SVT (II)
Study of more detailed striplets performance in high background (occupancy >= 10%) just started with Fastsim. …)
Background simulation:
Rates in strip layers 1-5 increased by a factor 3 after a bug was discovered, more checks ongoing. Layer0 was not affected.
Mechanics:
Progress in the design of striplets modules for Layer0 & definition of the full envelop for the entire SVT.
New manpower from UK (QM) on the design of the SVT mechanics (support cones and space frames). Fruitful meeting in May in Pisa to get started
Progress on HDI & Peripheral Electronics design
SuperB Workshop and Kick-Off Meeting - Elba, May 31, 2011

4. Pixel for Layer0 (I)
Clearer definition of requirements for Layer0 pixels:
Physics:
Resolution of um in both coordinates
Total material budget <= 1% X0
Radius ~ cm
Background (x5 safety included)
Rate ~ MHz/cm2 depends stronlgy on radius and sensor thickness
Timestamp of 1 us  5-10 Gbit/s per module
TID ~ 15Mrad/yr
Equivalent neutron fluence: n/cm2/yr
Standard CMOS MAPS marginal
Several options still open and under development  decision on technology in 2013
Hybrid pixels: more mature and rad hard but with higher material budget
R&D on FE chip 50x50 um pitch with fast readout ongoing (INFN – SuperB SVT group)
Pixel module design with ~ 1% X0 with present technology
Evaluate reduction of material in silicon & pixel bus:
CMOS MAPS: newer technology potentially very thin, readout speed and rad hardness challenging for application in Layer0.
R&D on DNW MAPS with sparsified fast readout well advanced (INFN – SuperB SVT group)
New submission in July with INMAPS CMOS process with high resistivity substrate & quadruple well to improve radiation hardness & charge collection efficiency.

5. SuperB Workshop and Kick-Off Meeting - Elba, May 31, 2011
Pixel for Layer0 (II)
Other groups interested in MAPS option for Layer0:
RAL (F. Wilson’s talk), Strasbourg. (I. Ripp’s talk)
Preparation for September 2011 pixel testbeam ongoing: hybrid pixel system, CMOS MAPS with vertical integration, irradiated MAPS ….
SuperB Workshop and Kick-Off Meeting - Elba, May 31, 2011

6. SuperB Workshop and Kick-Off Meeting - Elba, May 31, 2011

7. A few comments on key issues
V. Re
SuperB Workshop and Kick-Off Meeting - Elba, May 31, 2011

8. SuperB Workshop and Kick-Off Meeting - Elba, May 31, 2011
Background studies
The background-linked occupancy is a main concern, not only in layer0, but also in layers 1-5
This has a major impact on design choices for the readout chips for strip detectors:
Signal peaking times in analog section
Digital readout architecture (could be derived from pixels), clock frequency and time stamp resolution
Crosscheck background values with Belle-II
dE/dx studies also ongoing .
V. Re
SuperB Workshop and Kick-Off Meeting - Elba, May 31, 2011

9. SuperB Workshop and Kick-Off Meeting - Elba, May 31, 2011
V. Re
SuperB Workshop and Kick-Off Meeting - Elba, May 31, 2011

10. Efficiency vs peaking time in two different background conditions
No safety factor
Safety factor of 5 L5 L2 L5 L3 L3 L2 L4 L4 L1 L1 L0 L0
97.6% eff Tp(L1)=74 ns
97.6% eff Tp(L1)=15 ns

11. Readout chip for strips
~hit_rate * trig_latency
Sparsifier
strip #127 FE
ADC
Or ToT
Ctrl
logic
Buf #k
...
Buf #1
strip #0 FE
ADC
Or ToT
Ctrl
logic
Buf #k
...
Buf #1
BUF #1
Triggered hits only
readout/slow control

12. Efficiencies vs rate and dead times
Layer
CD [pF]
tp [ns]
ENC from RS [e rms]
ENC [e rms]
Hit rate/strip [kHz]
MMC
Efficiency
11.2 25
220
680
2060
(0.732) 1
26.7 50
650
1190
687
0.917
100
460
930
0.841 2
31.2
830
1400
422
0.948 3
45.8
1480
2130
325
0.960 4
52.6
1000
340
820 47
0.893 5
67.5
500
1010 28
0.934
Conditions: 20 buffers, 150 kHz trigger rate, 300 ns time window for all layers.

13. Data / Power Chain Several critical items have to be developed
Design choices also affect front-end chip design.
For a better power distribution system, the chips could integrate DC-DC converter, voltage regulator,..
La Biodola 2011

14. HDI … looking at Babar
The HDI must keep some/all the functionalities previously implemented:
1. Analog and digital powers. At least two different power supplies: analog and digital.
2. Two different current return, one for the digital current (DGND) and one for the analog current (AGND)
3. Each power line must be locally filtered
4. Two redundant sets of differential clock and command lines must given to all the chips and terminated so as to match with the characteristic impedance of the “tail”
5. Redundant differential data lines must be connected
6. Each HDI must host and provide connections to one resistive temperature monitor.
…. More
+ High speed data need to be transferred on the HDI
Data formatted from FE to “Data Encoder”
16:1 LOC 1 Serializer
High density connector should be chosen to connect power and signals to the “tail”
(Berg, Panasonics, etc…). Height after matching ~ 1.2 mm
La Biodola 2011
Mauro Citterio

15. Module Striplets Sensor position Fixing buttons R-fi fanout
HDI
Fixing buttons
Front-end chips
Final solution –HDI in axial direction inclinated at 300 mrad, with front-end chips 30° oriented 15

16. MAPS L0 module Design
Al-kapton BUS
HDI is positioned on outer radius for better radiation damage conditions
HDI
Z-piece
MAPS chips
Input coolant
Microtube support
Necessary thermal-structural simulation to verify L0 module mechanical stability
Output coolant

17. Module MAPS supports summary
Carbon Fiber Pultrusion
Peek pipe
Dh=300 mm
The single base microchannel unit
A square CF micro-tube with an internal peek tube 50 mm thick used to avoid moisture on carbon fiber
Full micro-channel module
The total radiation length (*) of this support is 0.28 %X0
12.8 mm
700 mm
Support Cross Section
Net micro-channel module
Same dimensions of full micro-channel but vacancies of tubes in the structure.
The total radiation length (*) is 0.15 %X0
(*): Material of the support structure: ( All C.F. material + peek tube + Water) 17

18. Layer 0 pixels Several technology options under evaluation:
Hybrid pixels
CMOS MAPS
3D integration

19. Hybrid pixels: can they be thin?
Alice upgrade R&D

20. CMOS sensors: can they be fast, high rate and rad-hard?
Interest from IPHC-Strasbourg
Submission of a pixel matrix in the INMAPS process in July (APSEL architecture, fully-depleted epitaxial layer)

21. 3D integration: can it be effective for high performance pixels in the SuperB time scale?
Tezzaron devices with the 3D-IC consortium: 3D MAPS and 3D integrated circuits for the readout of high resistivity pixels
The AIDA project: a less aggressive approach to 3D could also be useful to SuperB SVT
3D wafer bonding made at Tezzaron; next steps are thinning, backside metallization and dicing
Work for a second submission is advanced, but we’ll wait for test results on the devices from the first run
Advanced pixel sensors based on 3D integration of 2 layers in heterogeneous technologies
“via last” process, 4-side buttable device with low density interconnections in the device periphery available from several vendors

22. Conclusions & Perspectives
New groups are joining; this will greatly help activities on sensors, chips, mechanics, system aspects
Transition from generic R&D to developments focused on SuperB SVT is necessary
Test beam in September 2011 with MAPS (ST, Chartered), hybrid pixels, striplets module, associative memories; if available, 65 nm MAPS, 3D MAPS. Work on DAQ for this test is on schedule.
V. Re
SuperB Detector Workshop - SLAC, Feb , 2008

23. SuperB Detector Workshop - SLAC, Feb. 14-16, 2008
Backup
V. Re
SuperB Detector Workshop - SLAC, Feb , 2008