1. Cache and Scratch Pad Memory (SPM)
Embedded Systems: System-Level Design and Modeling
Cache and Scratch Pad Memory (SPM)
Gunar Schirner

2. Memory Wall
The growing disparity of speed between CPU and memory outside the CPU chip
Bandwidth wall: limited communication bandwidth beyond chip boundaries
Solution
Memory hierarchy
Registers
Different levels of caches and/or SPM
Main memory

3. Outline Cache Design alternatives for cache SPM vs. Cache
Benefits and downsides
Design alternatives for cache
Cache locking
Scratch Pad Memory (SPM)
SPM vs. Cache
Organization
Characteristics
Improvements

4. Embedded Systems: System-Level Design and Modeling
Cache
Cache as the primary solution for memory wall
Small memories on or close to the CPU
> 50% of chip area
+ Faster than main memory due to being transparent to the SW
1~2 cycle access latency and imp
+ Improved average execution time
- Unpredictable Worst Case Execution Time (WCET)
- Power hungry
25% to 45% of total chip power for caches and peripherals in embedded systems
CPU
Internal ROM
Internal
SRAM
External DRAM
Gunar Schirner

5. Outline Cache Design alternatives for cache SPM vs. Cache
Benefits and downsides
Design alternatives for cache
Cache locking
Scratch Pad Memory (SPM)
SPM vs. Cache
Organization
Characteristics
Improvements

6. Design Alternatives for Cache with High WCET Predictability
Embedded Systems: System-Level Design and Modeling
Design Alternatives for Cache with High WCET Predictability
Solution1: cache locking
Control over the cache contents by the SW
- Power hungry caches and peripherals
- Cache pollution
Solution2: Scratch Pad Memory (SPM)
Small and fast on chip static RAMs mapped to the processor’s address space at a predefined address range
Static : SPM locations don’t change at runtime
Dynamic : SPM locations don’t change at runtime
Data allocation under SW control
Profiling to estimate reuse and put reused data in SPM
+ Low power dissipation due to simple circuitry controlled by the SW
Cache pollution: loading more data than it is necessary
{especially when the cache block size is larger than the data required }
Gunar Schirner

7. Outline Cache Design alternatives for cache SPM vs. Cache
Benefits and downsides
Design alternatives for cache
Cache locking
Scratch Pad Memory (SPM)
SPM vs. Cache
Organization
Characteristics
Improvements

8. SPM Organization vs. Cache Organization
No need for address translation
The SMP memory array is statically addressed
No need for availability checking
The comparator and the signal miss/hit acknowledging circuitry
Similarity between cache and SPM
Connected to the same address and data buses
Access latency of 1 ~ 2 processor cycle

9. SPM Characteristics vs. Cache Characteristics
Embedded Systems: System-Level Design and Modeling
SPM Characteristics vs. Cache Characteristics
Cache
Indirect, hardware-managed addressing
Inefficient, cache line based storage
SPM
Not globally addressable
Not globally visible
- Cache has to access to the tag table (as the virtual address has to be converted to physical address ) cache is tagged by physical address because using virtual address might cause aliasing and different address generated by different processes have the same virtual address
- in cache, we have capacity, cold and conflict miss - with direct direct cache more than one address might be mapped to the same cache clock ….conflict! - associativity could help to reduce the conflicts
- in cache only a specific range of work load is always accessed and they might have conflict with each other, while the other space is cache is available…..or cache might be polutted as cache is address by block ( large block to have locality) and some of data in a block might not be used….
SPM does not have glocal addressing and visibility … each core has its own SPM and cannot be visible/addressed by the others ….
 shared data has to be moved explicitly from spm1 to memory and from memory to spm2. while in cache, hw does it …
 one data in 3 spaces…
 programmer has to put all the data once In spm while the data might be used very much later
 in system with cache we have lazy write, do write when it is necessary and the processor is free…here it should be does at the moment
 no reuse…..
Gunar Schirner

10. SPM Improvement over Cache
ATMEL board
CACTI model
Same size of Cache and SPM
Different applications including bubble sort, quick sort, etc. with different size from 64byte to 2048 byte
On average
Energy improvement by 40%
Performance improvement by 18%
Area improvement by 33%

11. References
Rajeshwari Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan, and Peter Marwedel Scratchpad memory: design alternative for cache on-chip memory in embedded systems. InProceedings of the tenth international symposium on Hardware/software codesign (CODES '02). ACM, New York, NY, USA, DOI=
Einstein, A., B. Podolsky, and N. Rosen, 1935, “Can quantum-mechanical description of physical reality be considered complete?”, Phys. Rev. 47,
Rakesh Komuravelli, Matthew D. Sinclair, Johnathan Alsop, Muhammad Huzaifa, Maria Kotsifakou, Prakalp Srivastava, Sarita V. Adve, and Vikram S. Adve Stash: have your scratchpad and cache it too. SIGARCH Comput. Archit. News 43, 3 (June 2015), DOI=

12. Thank you!