1. Hybrid pixel detectors based on capacitive chip to chip signal transmission
Ivan Peric, Christian Kreidl, Peter Fischer
University of Heidelberg
ZITI – Institute for computer science
Chair: LS SUS

2. Motivations
… to avoid complex interconnection techniques and make the hybrid detectors as simple as possible
achieve small pixel sizes – for instance 25X25 µm2
design low-cost and large scale-modules

3. Standard (DC coupled) hybrid pixel detector
RO Chip
CSA
CSA
Bump
Sensor Chip
Sensor diodes – passive detector 

4. Capacitive coupled hybrid pixel detector (CCPD)
CSA
RO Electrode Cc
Sens. Electr.
Bias resistance – punch through structure, FOXFET
Sensor diodes – passive detector 

5. Capacitive coupled hybrid pixel detector (CCPD) with passive sensor
Sensor material is ionized
Charge is separated and stored on Cd
…which leads to a voltage drop on the sensor electrode
A small charge amount is pumped by Cc into RO CSA
which amplifies the signal
Technical difficulties:
1) Small signal transferred to SCA - QsensCc/(Cd+Cc)
2) Need for bias resistance on the sensor pixel
Back plane capacitance of receiver plate leads to decreased S/N
Technical difficulties can be most probably solved

6. Capacitive coupled hybrid pixel detector (CCPD) with active sensor
RO Chip
Receiver CS amplifier
Sensor CS amplifier
Active Pixel Sensor
Sensor diodes – n-wells

7. Capacitive coupled hybrid pixel detector (CCPD) with active sensor
sensor material is ionized and electrons collected by n-well
CSA amplifies the signal
and generates a large voltage signal on the sensor electrode
which then injects a large amount of charge through Cc into ROC
Capacitive transferred charge is amplified by RO CSA
Possible technology options for the active pixel sensor:
1) CMOS with epi layer – MAPS
2) DEPFET
3) New – high voltage CMOS
(possibility to use CMOS pixel electronics, potentially higher radiation tolerance than by standard MAPS, charge collection close to the chip surface – thinning, long term availability of the technologies)

8. Active sensor in high voltage CMOS – signal generation
Feedback
Sensor electrode
PMOS
NMOS
P-well
50 V
Bias
Cin Cf
Cin
Deep N-well Cf
P-depleted
Sensor electrode
-50 V
~10 μm
CMOS amplifier
0 V
P-undepleted
Pixel electronics
- 3.3 V
Potential energy (Electrons)/e

9. Active sensor in high voltage CMOS – signal collection
Feedback
Sensor electrode
PMOS
NMOS
P-well
50 V
Bias
Cin Cf
Cin
Deep N-well Cf
P-depleted
Sensor electrode
-50 V
~10 μm
CMOS amplifier
0 V
P-undepleted
Pixel electronics
- 3.3 V
Potential energy (Electrons)/e

10. Active sensor in high voltage CMOS – signal amplification
Sensor electrode
Feedback
PMOS
NMOS
P-well
50 V
Bias
Cin Cf
Cin
Deep N-well Cf
P-depleted
Sensor electrode
-50 V
~10 μm
CMOS amplifier
0 V
P-undepleted
Pixel electronics
- 3.3 V
Potential energy (Electrons)/e

11. Active sensor in high voltage CMOS – end of amplification
Sensor electrode
Feedback
PMOS
NMOS
P-well
50 V
Bias
Cin Cf
Cin
Deep N-well Cf
P-depleted
Sensor electrode
-50 V
~10 μm
CMOS amplifier
0 V
P-undepleted
Pixel electronics
- 3.3 V
Potential energy (Electrons)/e

12. Active sensor in high voltage CMOS – return to baseline
Feedback
Sensor electrode
PMOS
NMOS
P-well
50 V
Bias
Cin Cf
Cin
Deep N-well Cf
P-depleted
Sensor electrode
-50 V
~10 μm
CMOS amplifier
0 V
P-undepleted
Pixel electronics
- 3.3 V
Potential energy (Electrons)/e

13. CCPD1

14. CCPD1 properties Readout- and sensor-chip aligned by flip-chip placer
and glued onto each other
The chips are contacted by wire bonds
AMS 0.35 µm high-voltage CMOS technology used for both chips
Radiation-tolerant layout
Use of current mode logic …

15. CCPD1 wire bonds Sensor pixels Chip A chips Signal transmission Chip B
Readout pixels
Sensor pixels
Sensor electrode
E-field
Readout electrode
Readout pixels

16. Trigger-based readout
Cfb
Rfb
Readout electrode
Valid hit
DEn
DFF
Bus driver
Trigger B D Q
Sensor chip 1 A 2 C
CmpOut
FF2
Data-bus Cc
Timer
DFF
Thr
Hit
Reset
Noise hit is not accepted V3
A – receiver CSA
C – comparator
- Timer generates Hit some defined time after the threshold crossing moment
- Only “in time signals” flagged as hits
Thr
CmpOut
Delay
Hit
Trigger
Hit time window

17. Experimental results - sensor

18. MIP Spectra Monolithic pixel detector in high voltage CMOS - HVPix1
Full signals: 2000 e
Split signals: 1100 e
Monolithic pixel detector in high voltage CMOS - HVPix1
- Binary readout scheme with in-pixel comparators and threshold tuning
- Pixel size 55X55 µm2
- Small matrix
- Spectra measured by ToT
Monolithic pixel detector in high voltage CMOS - HVPixM
- analog readout scheme with simple 5T pixel electronics
- Pixel size 19X19 µm2
- 128X128 matrix
In chip ADCs
Pixels with signal and their neighbors have been readout and amplitudes summed
Number of hits
noise spectrum
1800 e
MIP spectrum
ADC counts

19. Experimental results – CCPD1

20. Test pulse detection efficiency and threshold dispersion
Response probability of all pixels in the matrix to test pulses that generate 890 e in the sensor
Threshold dispersion
The same threshold settings lead to 0 noise signals when 100 triggers are issued
Response probability
Number of pixels
890 e
Sigma 46 e
Mean: 753 e
0 e
Pixel number
Input referred threshold/e

21. CCPD1 module
connector
RO chip
Sensor
PCB
Wire bonds
Wire bonds

22. CCPD1 module Drawbacks:
connector
RO chip
Sensor
PCB
Drawbacks:
- Large readout chips needed – high costs, yield problems
- Gap pixels need special connections
- Mechanical complexity – two side wire bonding

23. CCPD2

24. Sensor concept Pixel sensor
Power and signals for ROC routed on the sensor
Sensor electrodes grouped in the active ROC areas by fan-in
ROCs placed by flip-chip
Space covered by ROCs
Bumps S -

25. Sensor concept S - S -
RO chip S - S -
Sensor
Sensor
Bump Cc

26. Module concept
Hybrid
ROC
sensor

27. Sensor concept - properties
Large sensors covered with small readout chips
Uniform pixels
Unequal size of sensor and readout cells “pixels”
Drawback – decreased Cc due to the space occupied by bumps
Digital lines to sensor crosstalk can be eliminated by gigabit-rate digital communication provided the pixel amplifiers have smaller bandwidth

28. Chip layouts Readout chip – 30X30 matrix 40X40 µm2 pixels
0.18 µm UMC RF CMOS
Sensor chip: active sensor pixels – 30X30 matrix
50X50 µm2 pixels
0.35 µm AMS high voltage CMOS

29. Experimental results – CCPD2

30. Cc measurement Cfs ? Cfr = 3fF ? ?! Cinj Cc CCPD2 CCPD1 signal measure
Vout [mV]
Vout [mV]
Simulated gain of the receiver ~ 1f/Cfr ~ 0.3
Measured gain of the sensor ~ Cinj/Cfs ~ 0.94
Vin [mV]
Vin [mV]
Vout [mV]
Measured gain of the whole detector ~ Cc X 0.3 X 0.94 = 0.33
CCPD2
CCPD1
Cc ~ 1.18 fF
Compare with
Cc ~ 10fF
Distance ~ 20 µm
Distance ~ 8 µm
εr = 3
Vin [mV]

31. Noise and spectral measurement
Number of signals
Noise: 83 e
Threshold: 321 e
Input signal [e]
Response probability
Co-60 β-spectrum
Preliminary
ToT/20ns

32. Conclusion
Two capacitive coupled hybrid pixel detector has been presented
The detectors use active pixel sensors in high voltage CMOS technology
The chips of CCPD1 are wire-bonded to PCBs
Readout chips of CCPD2 are connected to power/digital signal lines that are placed on the sensor chip by a few bump-bonds
Simple gold-bond bumping technology available in our lab has been used on die level
Sensor generates mean MIP signal of approximately 1800 e
Noise measured for both prototypes is ~ 80 e
Threshold dispersion (CCPD1) is ~ 50 e
CCPD2 concept allows implementation of low-cost large-area modules
As example, the production cost of the CCPD2 prototype is “only” 4800 €

33. Many novel detector concepts are possible with CCPDs

34. DEPFET as CCPD
ROC
DEPFET sensor
connector

35. CCPD with ultra thin sensor in high-voltage CMOS
ROC
18 µm
sensor
2cm
1cm

36. CCPD with ultra thin sensor in high voltage CMOS
1mm
ROC
0.5mm
25 µm