1. Electrical and Computer Engineering University of Cyprus 12-09-2007
LAB 2: MIPS
Electrical and Computer Engineering
University of Cyprus

2. INTRODUCTION
The MIPS processor, designed in 1984 by researchers at Stanford University.
Is a RISC (Reduced Instruction Set Computer) processor. Compared with their CISC (Complex Instruction Set Computer) counterparts (such as the Intel Pentium processors), RISC processors typically support fewer and much simpler instructions.
A RISC processor can be made much faster than a CISC processor because of its simpler design.

3. INTRODUCTION (…)
RISC processors typically have a load-store architecture.
Two instructions for accessing memory: a load (l) instruction to load data from memory and a store (s) instruction to write data to memory.
None of the other instructions can access memory directly.

4. Single Cycle Datapath for MIPS
Stage 5 PC
Registers
ALU
Instruction
Memory
(Imem)
Data
Memory
(Dmem)
Stage 1
Stage 2
Stage 3
Stage 4
IFtch
Dcd
Exec
Mem WB
ALU IM
Reg DM

5. STAGES OF EXECUTION IN MIPS
5 stage instruction pipeline
1) I-fetch: Fetch Instruction, Increment PC
2) Decode: Instruction, Read Registers
3) Execute: Mem-reference: Calculate Address R-format: Perform ALU Operation
4) Memory: Load: Read Data from Data Memory Store: Write Data to Data Memory
5) Write Back: Write Data to Register

6. SINGLE CYCLE DATAPATH Dmem Zero A L U Imem M u x << Read data4
<< 2
PCSrc
25:21
MemWrite
Read
Addr
Read Reg1 P C
Read data
Read data1
Zero
31:0
20:16
Read Reg2 A L U
Instruc-
tion
Address M u x
Read data2
Write Reg M u x
Imem
Dmem
Regs
Write Data
ALU-
con
Write Data
15:11 M u x
RegDst
ALU-
src
RegWrite
Sign Extend
MemRead
15:0
ALUOp

7. STAGE 1: INSTRUCTION FETCH
Fetches the next instruction.
It sends the contents of the PC register, which contains the address for the next instruction, to the instruction memory (1).
The instruction memory will then respond by sending the correct instruction.
This instruction is sent on to the next (instruction decode) phase.

8. STAGE 1: INSTRUCTION FETCH

9. STAGE 2: INSTRUCTION DECODE
Two main tasks: calculate the next PC and fetch the operands for the current instruction.
Three possibilities for the next PC:
for all instructions that are not branches or jumps, we must simply calculate PC+4 to get the address of the next instruction.
For jumps and branches (if the branch is taken), we might also have to add some immediate value (the branch offset) to the PC (ADDi). This branch offset is encoded in the instruction itself.
For the jr and jalr instructions, we need to use the value of a register instead.

10. STAGE 2: INSTRUCTION DECODE
MUX3 selects between the first two posibilities (+4 or +immediate), and
MUX1 (in the IF phase) selects between MUX3 and the third posibility (value from the register file).

11. STAGE 2: INSTRUCTION DECODE
The second main task is to fetch the operands for the next instruction.
These operands come from the register file for all but two instructions.
The two instructions that are the exception are jal and jalr. These two jump instructions save the address of the next instruction in a destination register, so instead of sending an operand from the register file, we need to send the contents of the PC+4.

12. STAGE 3: EXECUTION “Executes" the instruction.
Any calculations necessary are done in this phase. These calculations are all done by the ALU (Arithmetic and Logic Unit).
The ALU needs two operands. These either come from the ID phase and thus in turn from the register file (or PC+4 for jump and link instructions), or one operand comes from the ID phase and the other comes from the instruction register to supply an immediate value.

13. STAGE 3: EXECUTION

14. STAGE 4: MEMORY ACCESS
Store operands into memory or load operands from memory. So, for all instructions except loads and stores, the MA simply passes on the value from the ALU on to the WB stage.
For loads and stores, the MA needs to send the effective address calculated by the ALU to memory.
For loads, the memory will then respond by sending the requested data back.
For stores, we need to send the data to be stored along with the effective address, and the memory will respond by updating itself.

15. STAGE 4: MEMORY ACCESS

16. STAGE 5: WRITE BACK
It simply takes the output of the MA phase, and sends it back to the write back phase to store the result into the destination register.
For stores (and no-ops), the write-back does nothing.

17. ALU Some ALU operations: Big Picture: What’s in there?? How do we
arithmetic
logic
“comparison”
Big Picture:
What’s in
there??
How do we
build it??

18. ALU - LOGIC OPERATIONS R-type (add, sub) instruction format:
Logical Operations
Logic Operations
MIPS instructions
shift left
<<
sll $10, $16, 8
shift right
>>
srl $10, $16, 8
AND
&
and $3, $7, $8 OR |
or $3, $7, $8
R-type (add, sub) instruction format: op rs rt rd
shamt
funct
6 bits = 32
opcode st src 2nd src dest shift amount func > fields
 For shift instructions (shift left and shift right), the 1st source register is unused.

19. ALU – HARDWARE BUILDING BLOCKS

20. A SIMPLE ALU CELL A B
add/subt
1-bit FA
carry_in
carry_out
result op

21. TO SEE HOW TO IMPLEMENT A SIMPLE ALU UNIT SEE LAB RESOURSES AT THE COURSE SITE