1. Prof. Sin-Min Lee Department of Computer Science
Lecture 14
Midterm 2 Revision 2
Prof. Sin-Min Lee
Department of Computer Science

2. Subtract by Summation
Subtraction with complement is done with binary numbers in a similar way.
Using two binary numbers X= and Y=
We perform X-Y and Y-X

3. X-Y X=
2’s com. of Y=
Sum=
Answer=

4. Y-X Y=
2’s com. of X=
Sum=
There’s no end carry: answer is negative (2’s complement of )

5. How To Represent Signed Numbers
Plus and minus signs used for decimal numbers: (or +25), -16, etc.
For computers, it is desirable to represent everything as bits.
Three types of signed binary number representations:
signed magnitude,
1’s complement, and
2’s complement

6. 1. signed magnitude
In each case: left-most bit indicates sign: positive (0) or negative (1).
Consider 1. signed magnitude:
= 1210
Sign bit
Magnitude =
Sign bit
Magnitude

7. 2. One’s Complement Representation
The one’s complement of a binary number involves inverting all bits.
To find negative of 1’s complement number take the 1’s complement of whole number including the sign bit.
= 1210
Sign bit
Magnitude =
Sign bit
1’complement

8. 3. Two’s Complement Representation
The two’s complement of a binary number involves inverting all bits and adding 1.
To find the negative of a signed number take the 2’s the 2’s complement of the positive number including the sign bit.
= 1210
Sign bit
Magnitude =
Sign bit
2’s complement

9. Sign addition in 2’s complement
The rule for addition is add the two numbers, including their sign bits, and discard any carry out of the sign (leftmost) bit position. Numerical examples for addition are shown below.
Example:
In each of the four cases, the operation performed is always addition, including the sign bits.
Only one rule for addition, no separate treatment of subtraction. Negative numbers are always represented in 2’s complement. 9 9

10. Arithmetic Subtraction
A subtraction operation can be changed to an addition operation if the sign of the subtrahend is changed.
(±A) - (+B) = (±A) + (-B)
(±A) - (-B) = (±A) + (+B)

11. Arithmetic Subtraction
Consider the subtraction of (-6) - (-13) = +7. In binary with eight bits this is written as The subtraction is changed to addition by taking the 2’s complement of the subtrahend (-13) to give (+13). In binary this is =
Removing the end carry, we obtain the correct answer (+ 7).

12. Overflow
The detection of an overflow after the addition of two binary numbers depends on whether the considered numbers are signed or unsigned.
When two unsigned numbers are added, an overflow is detected from the end carry out of the most significant position.
In the case of signed numbers, the leftmost bit always represents the sign, and negative numbers are in 2’s complement form.
When two signed numbers are added, the sign bit is treated as part of the number and the end carry does not indicate an overflow.

13. Overflow Overflow example: +70 0 1000110 -70 1 0111010
= =

14. Overflow
An overflow cannot occur after an addition if one number is positive and the other is negative, since adding a positive number to a negative number produces a result that is smaller than the larger of the two original numbers.
An overflow may occur if the two numbers added are both either positive or negative.

15. Some commonly used components
Decoders: n inputs, 2n outputs.
the inputs are used to select which output is turned on. At any time exactly one output is on.
Multiplexors: 2n inputs, n selection bits, 1 output.
the selection bits determine which input will become the output.
Adder: 2n inputs, 2n outputs.
Computer Arithmetic.

16. Multiplexer
“Selects” binary information from one of many input lines and directs it to a single output line.
Also known as the “selector” circuit,
Selection is controlled by a particular set of inputs lines whose # depends on the # of the data input lines.
For a 2n-to-1 multiplexer, there are 2n data input lines and n selection lines whose bit combination determines which input is selected.

17. MUX
Enable
2n Data
Inputs
Data
Output n
Input
Select

18. (Only one O/P asserted at any time
Remember the 2 – 4 Decoder?
Sel(3) S1
Sel(2)
Sel(1) S0
Sel(0)
Mutually Exclusive
(Only one O/P asserted at any time

19. 4 to 1 MUX DataFlow Control D3:D0 Dout 4 4 2 - 4 Decoder Sel(3:0) 2
S1:S0

20. 4-to-1 MUX (Gate level) Control Section
Three of these signal inputs will always be 0. The other will depend on the data value selected

21. Multiplexer (cont.)
Until now, we have examined single-bit data selected by a MUX. What if we want to select m-bit data/words?  Combine MUX blocks in parallel with common select and enable signals
Example: Construct a logic circuit that selects between 2 sets of 4-bit inputs (see next slide for solution).

22. Example: Quad 2-to-1 MUX
Uses four 4-to-1 MUXs with common select (S) and enable (E).
Select line chooses between Ai’s and Bi’s. The selected four-wire digital signal is sent to the Yi’s
Enable line turns MUX on and off (E=1 is on).

23. Implementing Boolean functions with Multiplexers
Any Boolean function of n variables can be implemented using a 2n-1-to-1 multiplexer. A MUX is basically a decoder with outputs ORed together, hence this isn’t surprising.
The SELECT signals generate the minterms of the function.
The data inputs identify which minterms are to be combined with an OR.

24. Example F(X,Y,Z) = X’Y’Z + X’YZ’ + XYZ’ + XYZ = Σm(1,2,6,7)
There are n=3 inputs, thus we need a 22-to-1 MUX
The first n-1 (=2) inputs serve as the selection lines

25. Efficient Method for implementing Boolean functions
For an n-variable function (e.g., f(A,B,C,D)):
Need a 2n-1 line MUX with n-1 select lines.
Enumerate function as a truth table with consistent ordering of variables (e.g., A,B,C,D)
Attach the most significant n-1 variables to the n-1 select lines (e.g., A,B,C)
Examine pairs of adjacent rows (only the least significant variable differs, e.g., D=0 and D=1).
Determine whether the function output for the (A,B,C,0) and (A,B,C,1) combination is (0,0), (0,1), (1,0), or (1,1).
Attach 0, D, D’, or 1 to the data input corresponding to (A,B,C) respectively.

26. Another Example
Consider F(A,B,C) = m(1,3,5,6). We can implement this function using a 4-to-1 MUX as follows.
The index is ABC. Apply A and B to the S1 and S0 selection inputs of the MUX (A is most sig, S1 is most sig.)
Enumerate function in a truth table.

27. MUX Example (cont.) When A=B=0, F=C When A=0, B=1, F=C1
When A=B=0, F=C
When A=0, B=1, F=C
When A=1, B=0, F=C
When A=B=1, F=C’

28. MUX implementation of F(A,B,C) = m(1,3,5,6)

29. These pictures have errors.

30. 1 input Decoder Decoder O0 I O1
Treat I as a 1 bit integer i. The ith output will be turned on (Oi=1), the other one off.

31. 1 input Decoder O0 I O1

32. 2 input Decoder Decoder O0 I0 O1 O2 I1 O3
Treat I0I1 as a 2 bit integer i. The ith output will be turned on (Oi=1), all the others off.

33. 2 input Decoder I0 I1 O0 = !I0 && !I1 O1 = !I0 && I1 O2 = I0 && !I1

34. 3 Input Decoder
Decoder O0 I0 O1 O2 I1 O3 O4 I2 O5 O6 O7

35. 3-Decoder Partial Implementation
. . .

36. 2 Input Multiplexor Inputs: I0 and I1 Selector: S Output: O Mux
If S is a 0: O=I0
If S is a 1: O=I1
Mux I0 O I1 S

37. 2-Mux Logic Design S I0 I1
I0 && !S O
I1 && S

38. 4 Input Multiplexor Inputs: I0 I1 I2 I3 Selectors: S0 S1 Output: O MuxI0 1 I1 I2 I3 I3 S0 S1

39. One Possible 4-Mux
2-Decoder S0 I0 S1 I1 O I2 I3

40. Adder We want to build a box that can add two 32 bit numbers.
Assume 2s complement representation
We can start by building a 1 bit adder.

41. Addition We need to build a 1 bit adder
compute binary addition of 2 bits.
We already know that the result is 2 bits. A B O0 O1 1
This is addition! A
+ B
O0 O1

42. One Implementation A
A && B O0 B !A
(!A && B) || (A && !B) B O1 A !B

43. Binary addition and our adder1 1
Carry
01001
10110
What we really want is something that can be used to implement the binary addition algorithm.
O0 is the carry
O1 is the sum

44. What about the second column?1 1
Carry
01001
10110
We are adding 3 bits
new bit is the carry from the first column.
The output is still 2 bits, a sum and a carry

45. Truth Table for Addition
Carry In
Out
Sum 1

47. Synchronous Sequential Circuit with T Flip-Flop --
Figure 8.12

48. Timing Diagram
Figure 8.13

49. State Table and State Diagram

50. K-Maps for Example

51. Example 2.Synchronous Sequential Circuit with JK Flip-flops

52. Timing Diagram and State Table for Example 2

53. K-Maps for Example 2

54. Generating the State Table From K-maps -- Example 2

55. Example 3.Synchronous Sequential Circuit Synthesis

56. Introductory Synthesis Example -- Example 3

57. Flip-flop Input Tables -- Example 3

58. Generating the JK Flip-flop Excitation Maps -- Example 3

59. Clocked JK Flip-Flop Implementation -- Example 3

60. Application Equation Method for Deriving Excitation Equations -- Example 3

62. Registers
Two independent flip-flops with clear and preset