1. Topics Coarse-grained FPGAs. Reconfigurable systems.
Reconfigurable ASICs.

2. FPGA granularity Typical LEs implement a small amount of logic.
Waste a lot of space/power on connecting logic elements.
Specialized adder logic tries to solve this problem for a special case.
Can build FPGAs with larger elements.

3. Granularity issues How big is the logic element?
How flexible should it be?
What interconnection network is needed?
How do you program it?

4. Reconfigurable systems
Reconfigure logic on-the-fly:
application characteristics may change over time.
Issues:
Reconfiguration time.
Reconfiguration memory cost.
Power consumption.
Synthesis for reconfiguration.

5. PipeRench Reconfigurable pipeline:
Each stage of the pipeline can be reconfigured quickly and independently.
Allows virtual pipeline that is longer than physical pipeline.

6. PipeRench pipeline operation

7. RaPiD architecture Coarse-grained computational architecture:
Soft control can be reconfigured on every cycle.
Hard control can be reconfigured only in configuration mode.
Interconnect network allows computational elements to be arranged in pipelines.

8. RaPiD pipeline

9. Reconfigurable ASICs Problems with ASICs:
Mask cost.
Manufacturing time.
Solution---mix ASIC and FPGA:
Reconfigurable logic on bottom.
Custom wiring on top.