1. TODAY’S OUTLINE Introduction to Verilog Verilog coding format
Module declaration
Verilog Data Types
Sensitivity list
Numbers in Verilog
Comments in Verilog

2. Introduction to Verilog
Many companies uses Verilog
Can be divided into 3 types of Verilog
Structural – netlist format
Behavioural – mostly used for analog circuit
RTL – describes the functionality of circuit and synthesizable codes

3. What is RTL RTL – synthesizable codes
Some design tools in market capable to auto-generate RTL based on graphical modes
Graphical entry can be in the form of flowcharts, truth tables, state diagrams

4. Cont..
Example of tools widely used for RTL generation: Mentor Graphic’s HDL series
With good RTL coding styles, timing and area can be greatly optimized
It is therefore essential that any new designs coded by inexperienced designers be checked by experienced Verilog designers

5. Verilog simulators There are many Verilog simulators
Among the more user friendly and widely used is Mentor Graphics
ModelSim environment consists of:
Verilog editor
Verilog simulator
Waveform analysis
Design debugging
ModelSim

6. TODAY’S OUTLINE Introduction to Verilog Verilog coding format
Module declaration
Verilog Data Types
Sensitivity list
Numbers in Verilog
Comments in Verilog

7. Verilog format
Unlike VHDL that have entity, architecture and configuration, Verilog only have module declaration
The module declaration declares the name of the module being coded and have a list of all the interface signals

8. Module declaration All Verilog code starts with the keyword “module”
Purposely used to describe the name of a module together with interface signals
All Verilog code ends with the keyword “endmodule” for terminating the module declaration

9. Cont.. Example : module test (A,B,C,Y) //enter your verilog code
Specification
module name = test
input = A, B, C
output = Y
Verilog format
module test (A,B,C,Y)
//enter your verilog code
//more of your verilog code
endmodule

10. Cont..
The module declaration is then followed by the declaration of the direction of the interface signals:
input …….;
output ……;
inout …….;

11. Cont.. Example : module test (A,B,C,Y) input A,B,C; output Y;
Specification
module name = test
input = A, B, C
output = Y
Verilog format
module test (A,B,C,Y)
input A,B,C;
output Y;
//more of your verilog code
endmodule

12. Cont.. Example : module test (A,B,C,Y) input [2:0] A,B; input [7:0] C;
Specification
module name = test
input = A(3 bit), B(3 bit), C(8 bit)
output = Y(5 bit)
Verilog format
module test (A,B,C,Y)
input [2:0] A,B;
input [7:0] C;
output [4:0] Y;
//more of your Verilog code
endmodule

13. Verilog data types
Interface signals are declared as either type “reg” or “wire” (commonly used)
Other data types such as tri, wand, wor, integer, real, time etc.

14. Cont.. “reg” – able to hold a value in the Verilog code
– a signal being assigned values during certain circuit conditions

15. Cont.. “wire” – able to assign a value in the Verilog code
– real physical wire connection between two gates whereby the value on the wire is consistently updated (continuous)

16. When to use “reg” and “wire”
When using assignment of values in an “always” block, use “reg” declaration
When using “assign” statement, always use “wire” declaration

17. Examples module ANDgate (A, B, Y) input A, B; output Y; wire Y;
Data type - wire
Data type - reg
module ANDgate (A, B, Y)
input A, B;
output Y;
wire Y;
assign Y = A & B;
endmodule
module ANDgate (A, B, Y)
input A, B;
output Y;
reg Y;
(A or B)
begin
Y = A & B;
end
endmodule

18. Sensitivity list Sensitivity list is associated with an “always” block
Signals that will cause an evaluation of the “always” block MUST be included in the sensitivity list

19. Example module ANDgate (A, B, Y) input A, B; output Y; reg Y;
(A or B)
begin
Y = A & B;
end
endmodule
Sensitivity list
“always” block will
be evaluated whenever
there is a change in
the signals listed in
sensitivity list

20. Numbers in Verilog Numbers in Verilog can be represented as:
Real numbers
Integer numbers
Base numbers (binary, octal, hex, decimal)

21. Examples Real numbers Integer numbers module …… real A; A = 3.142345;
endmodule
module ……
integer A;
A = 3;
endmodule
Base numbers
module ……
integer A, B, C;
A = 4b’0101;
B = 5’o14;
C = 8’ha5;
D = 5’d14;
endmodule
Commonly used
in Verilog

22. Comments in Verilog
Many designers always neglect to put comments in the code
Comments is an important form of documentation on the functionality/objective of the code
It helps in making the code readable

23. Cont.. Single line comments begins with the symbol //
Multiple line comments begins with /* and ends with */

24. Examples module ANDgate (A, B, Y) input A, B; output Y; reg Y;
(A or B)
begin
Y = (A & B)|( A | B); /* (A and B) or
(A or B) */
end
endmodule
module ANDgate (A, B, Y)
input A, B;
output Y;
reg Y;
(A or B)
begin
Y = A & B; // A and B
end
endmodule

25. That’s all for today.
See u on Tuesday (18 July 2006)..