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Differences of 8086,80386,i7
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Differences of 8086,80386,i7 Architecture and Pin Diagram Parameter
80386DX i7 Year June 1978 October 1985 November 2008 No of Cores 1 4 Architecture 16bit 32bit 64bit Speed 5,8,10 MHz 16,20,25,33 MHz 2.66,2.80,2.93,3.06,3.20 GHz Address Bus 20bit 64/32bit Data Bus Operating Voltage 5V 1.4V Addressable memory 1MB 4GB 64GB Physical Memory Virtual Memory 64TB 240 bytes
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Differences of 8086,80386,i7 Architecture and Pin Diagram Parameter
Register Size 16 bit 32 bit 64 bit Instruction Queue Size 6 bytes 16 bytes 18 entries Pins available 40 pin DIP package 132 pins 1366 pins Technology HMOS CHMOS II Bi-CMOS Pipeline Capability Yes Instruction set 117 Instructions 129 Instructions Supports 8086,386 and SIMD instructions On chip cache -- 3 level cache per core L1(32KB), L2(256KB),L3(8MB) Support for micro-architecture Nehalem Power management
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Differences of 8086,80386,i7 Architecture and Pin Diagram Parameter
Operating Modes Maximum Mode Minimum Mode Real Mode Protected Mode Virtual 8086 Mode Compatibility Mode 64 bit Mode Memory Models Flat Memory Real Address mode Flat memory Segmented Memory Real Address Mode On chip FPU No Yes Superscalar Branch Prediction Overclocking Feature Multiprocessor Support Latency 4 6 15 Use Portable computing Desktops Desktops, Laptops
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Differences of 8086,80386,i7 Additional Features 80386
Architectural support for memory management Virtual addressing Segmentation and Paging Protection Mechanism Multitasking 2. i7 Intel Quick Path interconnect(QPI) Intel Turbo Boost Technology Smart Cache Intel virtualization Technology Hyper-threading support MMX instruction Set
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Differences of 8086,80386,i7 Register Set Parameter 8086 80386DX i7
General Purpose Registers 8 GPRS of 16 bit 8 GPRS of 32 bit 16 GPRS of 64 bit Instruction Pointer IP of 16 bit EIP of 32 bit RIP of 64 bit Segment Registers 4 of 16 bit 6 of 16 bit Stack Pointer 16 bit 32 bit 64 bit Flag Register Flag Register of 16 bit EFlags Register of 32 bit RFlags Register of 64 bit Control Register -- Debug Register Descriptor Table Register GDTR : 48 bits IDTR : 48 bits LDTR : 16 bits TR : 16 bits Selector : 16 bits GDTR : 80 bits IDTR : 80 bits
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Differences of 8086,80386,i7 Register Set Parameter 8086 80386DX i7
FPU Registers -- 8 Data Registers of 80 bits Status Register of 16 bits Control Register of 16 bits Opcode register of 11 bits IP register of 64 bits Data pointer register of 64 bit Tag register of 16 bits MMX Register 8 MMX Register of 64 bits 16 XMM Register of 128 bits MXCSR Register of 32 bits
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