1. Design and Documentation

2. Top-down Modular Design
Top-down design is a process in which a function is initially specified at a high level of abstraction and then decomposed into lower-level sub-functions, each of which is more concrete.
The decomposition process continues until the design is reduced to a set of functions, each of which is well defined and can be realized with a relatively simple circuit.
Hence, the design has been developed from the “top” level “down” to a level at which the individual modules are manageable.

3. complete the design
After all functions have been defined, each is realized with a circuit module that is designed, implemented, and tested individually.
The finished modules are then interconnected to complete the design.
This implementation process is often referred to as a bottom-up process, since it begins with the bottommost elements of the design and works toward the topmost function.

4. decomposition of a design
The decomposition of a design is often represented in the form of a tree structure.
Let us suppose that we wish to design a circuit for a temperature acquisition system in which temperatures are read from two sensors, with one of the two computations (min(A, B) and max(A,B)) performed on these values as selected by a 1-bit code S.
Select Code, S Output function
0 min(A,B)
1 max(A,B)

5. A tree structure
The root of the design tree is the top-level function, T, which represents the complete system.
Three basic functions are needed to implement the process control system:
a circuit to create digital input signals from the two sensors,
a circuit to perform the two computations on the two sensor values, and
a circuit to select the desired result as the system output, according to the selection code S.
Therefore, top-level block T is decomposed into second-level blocks T1, T2 and T3, representing the input, computation, and output functions, respectively.
Next, each of the second-level functions is examined.

6. Input function T1
Input function T1 must convert data from the two sensors in to binary numbers.
Therefore, function T1 is decomposed into two sub-modules: conversion circuits T11 for sensor A and T12 for sensor B.
Both of these functions represent modules that are not broken down into smaller circuits.
Functions that are not further decomposed are called leaf nodes of the design tree.

7. The computation function T2
The computation function T2 must generate two values: min(A,B), and max(A,B).
These two sub-functions are defined as T21 and T22.
The sub-function T21 is further decomposed into T211 which compares A and B, and T212, which selects one of A or B according to the result of the comparison..
The sub-function T22 is similarly decomposed into T221 and T222.

8. The output function T3
The output function T3 selects one of two values, according to the selection code S.
This can be done with a standard circuit module.
Therefore block T3 is a leaf node of the design tree.

9. Block Diagram From the design tree, a block diagram can be developed.
Each block in this diagram represents one of the leaf nodes of the design tree, with all block inputs and outputs.
After completion of the block diagram, the designer has the option to choose from a standard modules, previously-designed modules or to develop a new one for each block.
Many different modules have been developed and are available as standard functions that can be used as building blocks for complex digital circuits.
In VLSI design (CPLD and FPGA), commonly-used modules, or standard cells, are maintained in libraries of functions from which they can be selected and incorporated into designs as needed.
For developing circuit boards and other multi-chip systems, there are a number of standard modules available as MSI circuit components (74 series chips).

10. Design Tree T Temperature Acquisition System Top level or, Level 1 T1
Input Sensor Data T2
Compute Values T3
Select Output
Level 2
T11
Sensor A
T12
Sensor B
T21
min(A,B)
T22
max(A,B)
Level 3
T211
Compare
A & B
T212
Select
min
T221
Compare
A & B
T222
Select
max
Leaf nodes
Level 4

11. Block Diagram Sensors T2 Compute T11 T12 T211 T212 Select T221 T222
Convert A A
T12
Convert B B
T211
Compare
T212
Select
T221
Compare
T222
Select T1
Input
FunctionSelect T3
Select T3
Output Select
Output

12. Documentation

13. Documentation
A good documentation is essential for correct design and efficient maintenance of digital systems.

14. Documentation Standards
Specification - describes what the system is suppose to do, interfaces, functions, what results not how.
Block diagrams - pictorial description of the system’s major functional modules and their interconnections first step in hierarchical design
Schematic diagrams - formal specification of the electrical components of the system, their interconnections in details. Logic diagram + more.
Structured logic device description - HDL programs (ABEL, Verilog, VHDL) in the form of equations, tables, or state diagrams.
Timing diagrams - various logic signals as a function of time.
Circuit descriptions - a narrative text document that explains how the system works internally.

15. Block Diagram

16. Block Diagram do’s/don’ts

17. Gate symbols

18. DeMorgan equivalent symbols
Which symbol to use?
Answer depends on signal names and active levels.

19. Signal names
Each input and output signal in a logic circuit should have a descriptive alphanumeric label, the signal’s name.
A signal’s name indicates
an action that is controlled e.g., GO, PAUSE
a condition that it detects e.g., READY, ERROR
data that it carries e.g., INBUS[31:0]

20. Signal names and active levels
Each signal name should have an active level (HIGH or LOW) associated with it.
A signal is active high if it performs the named action or denotes the named condition when it is high.
A signal is active low if it performs the named action or denotes the named condition when it is low.
A signal is said to be asserted when it is at its active level.
A signal is said to be negated or deasserted when it is not at its active level.

21. Signal names and active levels
Signal names are chosen to be descriptive.
Active levels -- HIGH or LOW
named condition or action occurs in either the HIGH or the LOW state, according to the active-level designation in the name.

22. Example HIGH when error occurs Logic Circuit ERROR OK_L Logic Circuit
LOW when error occurs
ERROR_L
ERROR
ERROR1_L

23. Signal name, logic expression, and logic equation
A signal name is just a name - an alphanumeric label.
X, Y, Z, READY, RD_L, WR_L
A logic expression combines signal names using the operators of switching algebra - AND, OR, and NOT.
X+Y
A logic equation is an assignment of a logic expression to a signal name - it describes one signal’s function in terms of other signals.
Z = X+Y

24. Active Levels of Pins
When we draw AND or OR symbols, we think of the given logic function as occurring inside that symbolic outline and they have active-high inputs.
They require 1s on the input to assert (when it is at its active level) their outputs.

25. Active Levels of Pins
Similarly, we show the same logic elements with active-low input and output pins as follows:

26. Drawing Layout Inputs on the left Ouputs on the right
Flow of signals should be from left to right.

27. Example of Buses

28. Schematic diagrams
Details of component inputs, outputs, and interconnections
Reference designators
Pin numbers
Title blocks
Names for all signals
Page-to-page connectors

29. Example schematic

30. Flat schematic structure

31. Hierarchichal schematic structure

32. Other Documentation Timing diagrams Output from simulator
Specialized timing-diagram drawing tools
Circuit descriptions
Text (word processing)
Can be as big as a book (e.g., typical Cisco ASIC descriptions)
Typically incorporate other elements (block diagrams, timing diagrams, etc.)

33. Timing Diagrams for a combinational circuit

34. Timing specification for 74 series gates

35. Block Diagram xx

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