1. CRU PCIe usage 1 1

2. DMA engine firmware sofware super page #0 super page #2 DMA engine
start_add #0
super page #0
start_add #2
super page #2
DMA engine
start_add #1
super page #1
start_add #31
super page #31 2 2

3. DMA engine firmware sofware super page #0 super page #2 DMA engine
start_add #0
super page #0
start_add #2
super page #2
DMA engine
start_add #1
super page #1
start_add #31
super page #31
START ADD | SIZE 3 3

4. DMA engine firmware sofware super page #0 super page #2 DMA engine
start_add #0
super page #0
start_add #2
super page #2
DMA engine
start_add #1
super page #1
start_add #31
super page #31
START ADD | SIZE
START ADD | SIZE 4 4

5. DMA engine firmware sofware super page #0 super page #2 DMA engine
start_add #0
super page #0
start_add #2
super page #2
DMA engine
start_add #1
super page #1
start_add #31
super page #31
START ADD | SIZE
START ADD | SIZE
START ADD | SIZE 5 5

6. DMA engine firmware sofware super page #0 super page #2 DMA engine
start_add #0
super page #0
start_add #2
super page #2
DMA engine
start_add #1
super page #1
start_add #31
super page #31
START ADD | SIZE
START ADD | SIZE
START ADD | SIZE 6 6

7. SUPER PAGE SUPER PAGE feature 7 7
8 KB page
SUPER PAGE feature
multiple of 32 KB (firmware requirements)
super page is contiguous in memory (all the pages have consecutive addresses)
every page in the superpage is 8KB (firmware requirements)
8 KB page 7 7

8. PERFORMANCE super page size (KB) DMA throughput (GB/s) 32 2.1 64 4.396
6.4
128
6.9
256 8 8

9. DATA FLOW 32 KB ON CHIP MEMORY USER DATA DMA engine
DATA TO HOST MEMORY 9 9

10. PCIe usage 8 KB DMA acknowledge DATA 10 10
(data has been moved in the host memory)
DATA
8 KB 10 10

11. PCIe usage 8 KB DMA acknowledge DATA 11 11
(data has been moved in the host memory)
DATA
8 KB 11 11

12. PCIe usage 8 KB DMA acknowledge DATA
(data has been moved in the host memory)
DATA
8 KB
In this situation the firmware has to wait 1 acknowledgment from the DMA engine before overwriting the data in the memory 12 12

13. PCIe usage DMA acknowledge DATA 8 KB 1 13 13
(data has been moved in the host memory)
DATA
8 KB 1 13 13

14. PCIe usage Understanding the counters 14 14
there are 2 components in the DMA that control the data throughput:
DATA FLOW CONTROLLER : write the DATA in the ONCHIP MEMORY
DESCRIPTOR CONTROLLER : triggers the DMA engine to move the DATA into the host memory
we have 2 different counters in the firmware:
counts how many clock cycle we wait for at least 1 acknowledge from the DMA (how fast we can write)
counts the number of clock cycle between 2 DMA descriptors (how fast we can read) 14 14

15. Time between 2 DMA DESCRIPTORs
The readout of the value was taken every 1s over a long run (~1h)
1 CC = 4 ns
MEAN VALUE
292 cc = us
MAX VALUE
2639 cc = ~10 us 15 15

16. Time spent waiting for DMA ACK signal
The readout of the value was taken every 1s over a long run (~1h)
1 CC = 4 ns
MEAN VALUE
37 cc = 148 ns
MAX VALUE
2342 cc = ~9 us 16 16