1. 15-740/18-740 Computer Architecture Lecture 0: Announcements/Logistics
Prof. Onur Mutlu
Carnegie Mellon University

2. Summary First lecture: September 8 (Wed) Homework 0 – Part 1
Due September 8 (Wed)
Homework 0 – Part 2
Due September 10 (Fri)
First readings
Reviews due September 10
Project ideas and groups
Read, think, and brainstorm
Proposal due September 27

3. Agenda Syllabus Homework 0 Readings for first lecture
Course logistics, info, requirements
Homework 0
Readings for first lecture

4. Course Info: Who Are We? Instructor: Prof. Onur Mutlu onur@cmu.edu
Office: Hamerschlag Hall-A305
Office Hours: W 2:30-3:30pm (or by appointment)
PhD from UT-Austin, worked at Microsoft Research, Intel, AMD
Research:
Computer architecture
Many-core systems: shared resources, asymmetric multi-core
Memory systems
Interconnection networks
Hardware/software interaction and co-design
Fault tolerance
Hardware security
Algorithms and architectures for genomics

5. Course Info: Who Are We? Teaching Assistants
Vivek Seshadri
GHC 7517
Evangelos Vlachos
HH A312
Office hours TBD
Course Administrative Assistant
Bara Ammoura

6. Where to Get Up-to-date Course Info?
Website:
Blackboard: Linked from website
Lecture notes
Readings
Project info
Discussion boards – share information
Your
Me and the TAs

7. What Will You Learn?
Computer Architecture: The science and art of designing, selecting, and interconnecting hardware components and designing the hardware/software interface to create a computing system that meets functional, performance, energy consumption, cost, and other specific goals.
Traditional definition: “The term architecture is used here to describe the attributes of a system as seen by the programmer, i.e., the conceptual structure and functional behavior as distinct from the organization of the dataflow and controls, the logic design, and the physical implementation.” Gene Amdahl, IBM Journal of R&D, April 1964

8. Levels of Transformation
Microarchitecture
ISA
Programs
Algorithm
Problem
Circuits/Technology
Electrons
Runtime System
(VM, OS, MM)
User
ISA is the interface between hardware and software… It is a contract that the hardware promises to satisfy.

9. What Will You Learn?
Hardware/software interface and major components of a modern microprocessor
State-of-the-art as well as research proposals
Tradeoffs and how to make them
Emphasis on cutting-edge research
Hands-on research in a computer architecture topic
Semester-long project
How to design better architectures (not an intro course)
How to dig out information
No textbook really required
But, see the syllabus

10. An Example: Multi-Core Systems
Chip
CORE 0
L2 CACHE 0
L2 CACHE 1
CORE 1
SHARED L3 CACHE
DRAM INTERFACE
DRAM MEMORY CONTROLLER
DRAM BANKS
CORE 2
L2 CACHE 2
L2 CACHE 3
CORE 3
*Die photo credit: AMD Barcelona

11. Unexpected Slowdowns in Multi-Core
High priority
Memory Performance Hog
Low priority
What kind of performance do we expect when we run two applications on a multi-core system? To answer this question, we performed an experiment. We took two applications we cared about, ran them together on different cores in a dual-core system, and measured their slowdown compared to when each is run alone on the same system. This graph shows the slowdown each app experienced. (DATA explanation…)
Why do we get such a large disparity in the slowdowns?
Is it the priorities? No. We went back and gave high priority to gcc and low priority to matlab. The slowdowns did not change at all. Neither the software or the hardware enforced the priorities.
Is it the contention in the disk? We checked for this possibility, but found that these applications did not have any disk accesses in the steady state. They both fit in the physical memory and therefore did not interfere in the disk.
What is it then? Why do we get such large disparity in slowdowns in a dual core system?
I will call such an application a “memory performance hog”
Now, let me tell you why this disparity in slowdowns happens.
Is it that there are other applications or the OS interfering with gcc, stealing its time quantums? No.
(Core 0)
(Core 1)

12. Why the Disparity in Slowdowns?
Multi-Core
Chip
CORE 1
matlab
CORE 2
gcc L2
CACHE L2
CACHE
unfairness
INTERCONNECT
Shared DRAM
Memory System
DRAM MEMORY CONTROLLER
-In a multi-core chip, different cores share some hardware resources. In particular, they share the DRAM memory system. The shared memory system consists of this and that.
When we run matlab on one core, and gcc on another core, both cores generate memory requests to access the DRAM banks. When these requests arrive at the DRAM controller, the controller favors matlab’s requests over gcc’s requests. As a result, matlab can make progress and continues generating memory requests. These requests are again favored by the DRAM controller over gcc’s requests. Therefore, gcc starves waiting for its requests to be serviced in DRAM whereas matlab makes very quick progress as if it were running alone.
Why does this happen? This is because the algorithms employed by the DRAM controller are unfair.
But, why are these algorithms unfair? Why do they unfairly prioritize matlab accesses?
To understand this, we need to understand how a DRAM bank operates.
Almost all systems today contain multi-core chips
Multi-core systems consist of multiple on-chip cores and caches
Cores share the DRAM memory system
DRAM memory system consists of
DRAM banks that store data (multiple banks to allow parallel accesses)
DRAM memory controller that mediates between cores and DRAM memory
It schedules memory operations generated by cores to DRAM
This talk is about exploiting the unfair algorithms in the memory controllers to perform denial of service to running threads
To understand how this happens, we need to know about how each DRAM bank operates
DRAM
Bank 0
DRAM
Bank 1
DRAM
Bank 2
DRAM
Bank 3

13. What Do I Expect From You?
Required background: basic architecture (18-447), basic compilers, basic OS, programming
Learn the material
And, research it
Do the work & work hard
Ask questions, take notes
Read and review the assigned research papers & readings
Discuss/critique them online with peers and us
Write your critique/review online
Study in groups, but submit your own work
Start early and focus on the research project
If you want feedback, come to office hours

14. How Will You Be Evaluated?
Homeworks, Online Reviews, Quizzes: 10%
Research Project: 35%
Midterm I: 20%
Midterm II (comprehensive): 35%
Our evaluation of your performance: 5%
Participation+discussion counts

15. More on Homeworks and Policy
Content from lectures, readings, project, discussions
All homeworks must be your own work
Research project in groups
Late policy: Maximum five late days total
Honor code: No tolerance on cheating, academic dishonesty
See syllabus

16. Research Project
Your chance to explore in depth a computer architecture topic that interests you
Perhaps even publish your innovation in a top computer architecture conference.
Start thinking about your project topic from now!
Interact with me and Evangelos & Vivek
Groups of 2-3 students (will finalize this later)
Proposal due: Sep 27

17. Homework 0 Part 1 Part 2 Paper Reviews
Our way of getting to know about you fast
Due Sep 8
Part 2
Four readings
One cache question
Due Sep 10
Paper Reviews
Write brief reviews online for the four readings
Key ideas, strengths, weaknesses, challenges, what did you learn? Are the statements valid, interesting, exciting?

18. Summary First lecture: September 8 (Wed) Homework 0 – Part 1
Due September 8 (Wed)
Homework 0 – Part 2
Due September 10 (Fri)
First readings
Reviews due September 10
Project ideas and groups
Read, think, and brainstorm
Proposal due September 27