1. DCH FEE STATUS Level 1 Triggered Data Flow FEE Implementation &
28 chs chamber prototype FEE for CC study
G. Felici
G. Felici
CALTECH - SuperB Workshop - December 2010

2. CALTECH - SuperB Workshop - December 2010
Outline
DCH TRIGGERED DATA FLOW – STANDARD RO (NO – CC)
Trigger & OL Specs (reminds)
ADB main blocks & data frame (remind)
FE readout architecture
Single channel multi-events and single event readout simulation
Cluster Counting with the local derivative method
Circuit block diagram & digitized output samples
Chamber prototype front-end for Cluster Counting & standard RO
Conclusions
G. Felici
CALTECH - SuperB Workshop - December 2010

3. Trigger & OL specs (remind)
System
Trigger rate (average): 150 kHz
Trigger (fixed) latency : ≈ 6 μs
Data OL BW : 16 2 Gbits/sec
ECS OL BW : 16 2 Gbits/sec
Trigger OL BW : Gbit/sec
Trigger spacing (min) > 36 ns (sampling frequency = 56 MHz)
Trigger burst : 4 events (check other sub-detector ..)
Detector
Number of cells (guess): ≈ 9216
Chamber occupancy : 15% (Inner layers)
Chamber gain : 5 105
Sense wire parasitic (CD) ≈ 25 pF
G. Felici
CALTECH - SuperB Workshop - December 2010

4. ADB main blocks & data frame (remind)
Single Channel ROIB Digitizer (ADB)
Trigger Latency Time + n samples
3 Events RO Buffer
56 MHz sampling rate
LPF
FADC n 1 ? 4 3 2 1
DISCR
TDC
32 samples (≈ 570 ns) must allow DC full signal development and include distribution time jitter
NB : sampling rate can be reduced to manage slower drift time in DC still fulfilling dE/dx resolution requirement
SAMPLING
Trigger
7 MHz
Digitized Data Frame Example
ADC # 31
ADC # 30
ADC # 29
ADC # 28
ADC # 27
ADC # 26
ADC # 25
ADC # 24
ADC # 23
ADC # 22
ADC # 21
ADC # 20
ADC # 19
ADC # 18
ADC # 17
ADC # 16
ADC # 15
ADC # 14
ADC # 13
ADC # 12
ADC # 11
TDC # 2
ADC # 9
ADC # 8
ADC # 7
TDC # 1
ADC # 5
ADC # 4
ADC # 3
ADC # 2
ADC # 1
ADC #
Position inside the frame  coarse time measurement (5 bits)
Content  fine time measurement (6 bits)
G. Felici
CALTECH - SuperB Workshop - December 2010

5. FE readout architecture
implemented and simulated on a SPARTAN 6 device (XC6SLX150T-FGG900)
DISTRIBUTED RAM
16 bits – 4 events (128 words)
Trigger Latency Time + n samples (Dual-port memory)
BLOCK RAM
16 bits – 1024 words
RO buffer
32 word block data readout n 2 1
DATA RO SM
(FEX)
Pushing mode
Ev4
Ev3
Ev2
Ev1
Sampled data
Triggered Data Bus OL
(counter L1) - Latency
Read ADDR
ADDR
Sampling clock
COUNTER (0 – n)
ADDR
DISTRIBUTED RAM
10 bits – 16 words
FiFO Empty
L1 FIFO
L1 (synchronized by sampling clock)
FiFO Read
Data (counter L1)
SINGLE CHANNEL RO IMPLENTATION
G. Felici
CALTECH - SuperB Workshop - December 2010

6. FE readout architecture
4 L1 events spaced 36 ns (sampling CLK = 58 MHz – Memory RO CLK = 116 MHz)
ADC sampling clock
4 consecutive L1 trigger spaced 36 ns
continuous input sampling
1st 32 samples RO
2nd 32 samples RO
Single event 58 MHz and 116 MHz
ADC sampling clock
L1 trigger
ADC sampled signal (example)
Dual Port Memory sample readout
G. Felici
CALTECH - SuperB Workshop - December 2010

7. Cluster Counting with the local derivative method
G. Felici
CALTECH - SuperB Workshop - December 2010

8. Local Derivative Method
BUFFER
AMPLIFIER
DISCRIMINATOR
BUFFER
DELAY ( ns)
VTH
VTH close to the system noise limit
COLLIMATED IRON SOURCE
G. Felici
CALTECH - SuperB Workshop - December 2010

9. Chamber prototype front-end for Cluster Counting & standard RO
G. Felici
CALTECH - SuperB Workshop - December 2010

10. 28 chs chamber proto - ON & OFF detector electronics
GROUND PLANE
OFF-DETECTOR FEE - 1 OF 28 CHS
7 CHS BOARDS
TEST PULSE
PREAMPLIFIER BOARDS
OUT SIGNAL
ON-DETECTOR FEE - 1 OF 7 CHS
G. Felici
CALTECH - SuperB Workshop - December 2010

11. CALTECH - SuperB Workshop - December 2010
Conclusions
We have started FE readout architecture simulation (as planned in the previous WS). A single readout channel has been implemented on a SPARTAN 6 device and fully simulated for consecutive triggers spaced 36 ns (up to 4 triggers). An example of (a very simple) reconstructed waveform has been also shown.
SIMULATION NEXT STEP
FEX implementation for a single channel
Two continuous cathode single channel detectors (.4 and 2.7 mt length)instrumented with local derivative method have been set up and preliminary results (for the 2.7 mt detector) have been shown.
28 chs chamber prototype front-end design has been started. Front-end will be split in two sections. The first one (on-detector) will be based on a wide band transimpedance preamplifier, while the second one (off-detector electronics) will include local derivative circuit and outputs for ADC/TDC and as well.
G. Felici
CALTECH - SuperB Workshop - December 2010