1. 基于FPGA的时间数字转换标准化模块设计
范欢欢

2. Outline Implementation of FPGA TDC FPGA TDC Timing Performance
Available TDC Modules
Plan

3. The Principle of the FPGA TDC
Coarse Counter (Coarse Time)+Time Interpolation within
one clock period (Fine Time)

4. Implementation of the Time Interpolation
Time Interpolation with the delay of Carry lines
a) Carry-in in a CLB
c) Carry chain of a multi-bit adder
b) Rout in a SLICE

5. ~ 10 ps Bin Size (Effective) , <10 ps RMS A Modified Wave Union TDC
FPGA USTC
~100 ps Bin Size, 50 ps RMS ; In the year 2005
TNS Vol.53, Issue 1, Part 2, pages:
Time interpolation with the dedicated Carry lines
~50 ps Bin Size, < 20 ps RMS ; In the year 2009
TNS Vol.57, Issue 2, Part 1, pages:
With Several Compensation Strategies: self-test, Temperature
compensation
Up to the present
~ 10 ps Bin Size (Effective) , <10 ps RMS
A Modified Wave Union TDC
TNS Vol.58, Issue 4, Part2, pages:

6. Principle of the 10-ps FPGA TDC
Wave Union Launcher
INV+Delay+MUX

7. The 10-ps Multi-Averaging TDC
Key Parameters
• A total of 9 channels, with ~60% logic utilization (XC4VFX60)
• 24 Bits Coarse Counter reaches ~168 ms dynamic range per channel
• RMS timing below 10 ps, Bin size ~ 10 ps (N=4)
No additional requirement on carry-chain length
User-assignable Averaging Times (N)
TDC Bin size, RMS timing precision vs. N

8. Signal Processing of the Raw TDC Time
N times Oscillation

9. Signal Processing of the Multi-averaging TDC
RMS timing precision (σdelay) vs. N
• Non-uniformed distribution of the carry chain delay (σcell )
• Random uncertainty of the oscillation period (σosc )
• Other contributors, e.g. the steady of the clock (σother)
Three possible cases:
• Case 1: σosc << σcell
• Case 2: σosc ≈ σcell The best
• Case 3: σosc >> σcell

10. Simulation and Test 3 2 1 Simulation Test: RMS vs. N
Case 1: σosc << σcell
Case 2: σosc ≈ σcell
Case 3: σosc >> σcell 3
Simulation 2
Actual implementation falls in to Case 2 1
Test: RMS vs. N

11. Signal Processing of the Multi-averaging TDC
Bin size vs. N
Effective Bin size:
Scales as 1/N
No Averaging
N=4
N=8

12. Determination of Averaging Times N
Pros and Cons
√ Larger N results in smaller bin size, lower timing precision
× Larger N results in larger dead time
~ (N+1) * TCLK ,
Trade-off should be made between TDC timing performance and N
No Averaging
N=4

13. FPGA TDC Modules Available
~50 ps RMS, 100 ps Bin
• NIM, USB, other platforms
• 16 Channels, ~170 ms Dynamic range
• single-ended input, Range from -5V~5V, with on-board fast discriminator

14. FPGA TDC Modules Available
TDC Logic IP Design, + Trigger Matching
• ~170 ms Dynamic range
• LVDS input
• 9 Channels in XC4VFX60,
• ~20 ps RMS, 50 ps Bin cost less than 20% of the total logic elements (total 50k LUTs and Registers available in XC4VFX60)
• < 10 ps RMS, 12 ps Bin, cost 60% of the total logic elements
Based on the TDC implemented in FPGA, we have made a variety of FPGA TDC modules.
Up to the present, we already have TDC modules of 20 ps on different platforms, such as NIM, USB.
We are now planning a new TDC module of 10 ps on the platform of PXI and VME.

15. FPGA TDC Modules Available
Virtex 5 FPGA TDC Modules (PXI, VME)
• ~15 ps RMS, 30 ps Bin
• ~170 ms Dynamic range
• LVDS input, 16 channels, on PXI, VME
RMS: 14 ps

16. FPGA TDC Test Setup
FPGA
RMS: 14 ps

17. FPGA TDC Test Setup
FPGA
count
Delay(ps)

18. FPGA TDC Modules Available
Implementation of TOT function：
ch1
ch2
Hit
count
CLK
Hit
~ Hit
Measure leading

19. plan PXI/VME接口的FPGA TDC： Trigger matching implementation
16channels TOT implementation

20. Thank you!

21. The result of trailing measure