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Andreas Hoffmann Andreas Ropers Tim Kogel Stefan Pees Prof

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1 Modeling of Embedded Processors with LISA for Architecture Exploration and System-Level Simulation
Andreas Hoffmann Andreas Ropers Tim Kogel Stefan Pees Prof. Heinrich Meyr Integrated Signal Processing Systems (ISS) Aachen University of Technology Germany

2 Exploration by Iterative Improvement
regs data mem prog pipeline control IF/ID ID/EX EX/WB seq profiling Cycle-based simulators performance modelling verification criterias met ? Application code HLL-compiler simulator assembler/ linker Complete tool-suite required assembler, linker

3 SW Development Tools Building a custom tool-set
extremely error-prone tedious and lengthy process difficulty of matching the tools to an abstract model of the processor architecture verification against golden model not suited for rapid design space exploration and stepwise refinement of the target architecture

4 Fast Processor Simulation
hardware-based models not applicable for SOC designs usually not available - no silicon processor simulators (interpretive) standard technique of commercial simulators provided by semiconductor vendors too slow for multiple iterations with large test vector sets compiled processor simulators translate object code of application to executable simulation implementation for different DSP architectures: typical speed-ups: 30x - 150x faster simulation retargetability simulator

5 Example: SW Development
Verification of GSM coder/decoder (1 minute speech) Simulation speed TI C54x simulator (2.2k insns/s) days insns of the workstation for insn of the C54x DSP! fast C54x Simulator (160k insns/s) 1 h

6 Compiled vs. Interpretive Simulation
IF1 ID1 OF1 EX1 interpretive simulation IF2 ID2 OF2 EX2 IF3 ID3 OF3 EX3 IF4 ID4 OF4 EX4 object code object code compiled simulation EX1 simulation compiler EX2 EX3 EX4

7 Abstraction Levels SW level instruction-based model instruction set
cycle-count accurate instruction set architecture level model DSP pipeline cycle-based ASIC DSP µC memory system level model

8 Model Components of SW Tools
Memory model registers, memories bit widths, ranges Resource model hardware resources resource requirements of operations Behavioral Model abstracted hardware activities (various levels) changing the system state Instruction-set model composed of valid HW operations assembly syntax instruction word coding instruction semantics Timing model activation sequence of hardware operations pipeline

9 Existing Description Languages
instructions-set based languages (nML, Maril, etc ...) only latency annotation no pipeline support higher abstraction levels Gap support for compiled processor simulation? HDLs (VHDL, Verilog, ...) structure-oriented, hardware-details low simulation efficiency missing instruction-set model lower abstraction levels

10 LISA processor description

11 LISA Approach LISA description processor architecture (HW) instruction
set (SW)

12 LISA Description Components - HW
Processor Architecture Description mixed behavioral/structural model based on C/C++ enriched by timing information based on extended reservation tables allow instruction/cycle/phase-accurate models predefined pipeline operations addressing compiled simulation compile-time statements processor architecture (HW) idea: cut-down HDL capabilities to synchronous models

13 LISA Description Components - SW
Instruction Set Description instruction word coding variable widths multiple words assembly syntax instruction-level parallelism instruction semantics distinction between semantics and behavior instruction set (SW) idea: extend the nML approach

14 retargetable development tools

15 Retargetable Environment
LISA processor description generic processor model processor model (intermediate representation) generator generator generator generator generator SuperSim (simulator) co-simulation (VHDL) assembler/ linker VHDL synthesis HLL compiler debugger

16 Retargetable Simulator
architecture specific architecture specific application specific LISA compiler LISA processor description simulation compiler generator simulation compiler application program generic processor model compiled simulator simulation table simulation library simulation library generator

17 Target-Independent Debugger

18 case study: cycle-based model TI C6201

19 LISA Example: TI C6201 Model
cycle-accurate model CPU core, pipeline, program & data memories 53 resources, 267 operations 9978 lines of LISA and C code (253kB) (incl. comments & empty lines) design effort: 4 weeks CPU core 2 weeks memory interface

20 Simulation of TI C6201 model
simulation speed [instructions/s] speed-up

21 summary & outlook

22 LISA processor models Processors described with LISA:
Texas Instruments TMS320C6x (cycle accurate) Texas Instruments TMS320C54x (cycle accurate) Analog Devices ADSP21xx (cycle accurate) ARM 7 TDMI (instruction set) DLX architecture (cycle accurate)

23 Outlook future research
modeling & simulation of processor architectures extend pool of processor architectures (DSP & µC) model abstraction generation of higher-level processor models HW synthesis of pipeline control and instruction decoder automatic test pattern generation power estimation retargetable compilation

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