1. Chapter 4: Introduction to Assembly Language Programming

2. Overview General introduction
Introduction to Assembly Language Programming
Current Program Status Register (CPSR)
N (negative) bit
Z (zero) bit
C (carry) bit
V (overflow) bit
Data processing operations
Arithmetic operations (add subtract etc)
Logical operations (and, or etc)
Register Moves (mov etc)
Comparison Operations (cmp etc)

3. 1) General introduction – of ARM Features
Load-Store architecture
Load (from memory to Central processing Unit CPU registers)
Store (from CPU registers to memory)
Fixed-length (32-bit) instructions
Each machine instruction is 32-bit, no more no less.
Conditional execution of ALL instructions
The condition register (CPSR) holds the result condition: the result is +ve, -Ve, overflow, etc

4. Registers Registers in a CPU store temporary data in the processor
Transfers to/from memory (i.e. Load/Store) are relatively slow
Operations involving registers only are fast

5. Data Sizes and Instruction Sets
The ARM is a 32-bit architecture.
When used in relation to the ARM:
Byte means 8 bits
Halfword means 16 bits (two bytes)
Word means 32 bits (four bytes)
Most ARM’s implement two instruction sets
32-bit ARM Instruction Set
16-bit Thumb Instruction Set
The cause of confusion here is the term “word” which will mean 16-bits to people with a 16-bit background.
In the ARM world 16-bits is a “halfword” as the architecture is a 32-bit one, whereas “word” means 32-bits.
Java bytecodes are 8-bit instructions designed to be architecture independent. Jazelle transparently executes most bytecodes in hardware and some in highly optimized ARM code. This is due to a tradeoff between hardware complexity (power consumption & silicon area) and speed.

6. Processor Modes The ARM has seven basic operating modes:
User : unprivileged mode under which most tasks run
FIQ : entered when a high priority (fast) interrupt is raised
IRQ : entered when a low priority (normal) interrupt is raised
Supervisor : entered on reset and when a Software Interrupt
instruction is executed
Abort : used to handle memory access violations
Undef : used to handle undefined instructions
System : privileged mode using the same registers as user mode
The Programmers Model can be split into two elements - first of all, the processor modes and secondly, the processor registers. So let’s start by looking at the modes.
Now the typical application will run in an unprivileged mode know as “User” mode, whereas the various exception types will be dealt with in one of the privileged modes : Fast Interrupt, Supervisor, Abort, Normal Interrupt and Undefined (and we will look at what causes each of the exceptions later on).
NB - spell out the word FIQ, otherwise you are saying something rude in German!
One question here is what is the difference between the privileged and unprivileged modes? Well in reality very little really - the ARM core has an output signal (nTRANS on ARM7TDMI, InTRANS, DnTRANS on 9, or encoded as part of HPROT or BPROT in AMBA) which indicates whether the current mode is privileged or unprivileged, and this can be used, for instance, by a memory controller to only allow IO access in a privileged mode. In addition some operations are only permitted in a privileged mode, such as directly changing the mode and enabling of interrupts.
All current ARM cores implement system mode (added in architecture v4). This is simply a privileged version of user mode. Important for re-entrant exceptions because no exceptions can cause system mode to be entered.

7. Register Organization Summary
User
FIQ
IRQ
SVC
Undef
Abort r8 r9
r10
r11
r12
r13 (sp)
r14 (lr)
r15 (pc)
cpsr r0 r1 r2 r3 r4 r5 r6 r7
User mode r0-r7, r15, and cpsr
User mode r0-r12, r15, and cpsr
User mode r0-r12, r15, and cpsr
User mode r0-r12, r15, and cpsr
User mode r0-r12, r15, and cpsr
Thumb state
Low registers r8 r9
Thumb state
High registers
r10
r11
r12
r13 (sp)
r13 (sp)
r13 (sp)
r13 (sp)
r13 (sp)
This slide shows the registers visible in each mode - basically in a more static fashion than the previous animated slide that is more useful for reference.
The main point to state here is the splitting of the registers in Thumb state into Low and High registers.
ARM register banking is the minimum necessary for fast handling of overlapping exceptions of different types (e.g. ABORT during SWI during IRQ). For nested exceptions of the same type (e.g. re-entrant interrupts) some additional pushing of registers to the stack is required.
r14 (lr)
r14 (lr)
r14 (lr)
r14 (lr)
r14 (lr)
spsr
spsr
spsr
spsr
spsr
Note: System mode uses the User mode register set

8. The Registers ARM has 37 registers all of which are 32-bits long.
1 dedicated program counter
1 dedicated current program status register
5 dedicated saved program status registers
30 general purpose registers
The current processor mode governs which of several banks is accessible. Each mode can access
a particular set of r0-r12 registers
a particular r13 (the stack pointer, sp) and r14 (the link register, lr)
the program counter, r15 (pc)
the current program status register, cpsr
Privileged modes (except System) can also access
a particular spsr (saved program status register)
The ARM architecture provides a total of 37 registers, all of which are 32-bits long. However these are arranged into several banks, with the accessible bank being governed by the current processor mode. We will see this in more detail in a couple of slides. In summary though, in each mode, the core can access:
a particular set of 13 general purpose registers (r0 - r12).
a particular r13 - which is typically used as a stack pointer. This will be a different r13 for each mode, so allowing each exception type to have its own stack.
a particular r14 - which is used as a link (or return address) register. Again this will be a different r14 for each mode.
r15 - whose only use is as the Program counter.
The CPSR (Current Program Status Register) - this stores additional information about the state of the processor:
And finally in privileged modes, a particular SPSR (Saved Program Status Register). This stores a copy of the previous CPSR value when an exception occurs. This combined with the link register allows exceptions to return without corrupting processor state.

9. Important registers at the moment
Register name
32-bit wide/ usage
R0-R12
General purpose registers
R14
Link register
R15
Program counter (PC)

10. Saved Program Status Registers (SPSRs)
The SPSRs are used to store the CPSR when an exception is taken.One SPSR is accessible in each of the exception-handling modes.
User mode and System mode do not have an SPSR because they are not exception handling modes.

11. The program counter(pc)
The program counter is accessed as r15 (or pc). It is incremented by one word (four bytes) for each instruction in ARM state, or by two bytes in Thumb state.
Branch instructions load the destination address into the program counter. You can also load the program counter directly using data operation instructions. For example, to return from a subroutine, you can copy the link register into the program counter using:
MOV pc,lr
During execution, r15 does not contain the address of the currently executing instruction. The address of the currently executing instruction is typically pc– 8 for ARM, or pc– 4 for Thumb.

12. The Current Program Status Register(CPSR)
The CPSR holds:
copies of the Arithmetic Logic Unit (ALU) status flags
the current processor mode
interrupt disable flags.
The ALU status flags in the CPSR are used to determine whether conditional instructions are executed or not.
On Thumb-capable processors, the CPSR also holds the current processor state (ARM or Thumb).

13. 2) Introduction to assembly language programming
The following is a simple example which illustrates some of the core constituents of an ARM assembler module:
operands
label
opcode
comment

14. General purpose register R0-R12 usage
Example:
An assemble instruction
Mov r0,#15
Convert hex to decimal : converter.php
Will move the value #15 (decimal) into register R0.
“Mov” means “to move”
R0 is register 0 (32-bit)
# (hash) means it is a direct value, defined by a number following #. 15 R0

15. Brach function (BL) is an instruction in ARM
BL = branch and link
Example:
BL firstfunc ; this instruction means
Content in R14 (link register) is replaced with content of R15(program counter=PC)+4.
Content of PC is replaced by the address of firstfunc

16. Exercise 1 What is Firstfun and what is the address of Firstfunc
Exercise 1 What is Firstfun and what is the address of Firstfunc? Fill in the shaded areas.
Address (H)
Comments
Before instruction is run
After instruction is run PC
start
All registers are rest to 0 here
R14=link
R15=PC R0 R1
Mov r0,#15
;Set up parameter
Mov r1,#20
BL Firstfunc
;Branch, call subroutine Firstfunc
SW1
Meaning stop here : Software interrupt (will be discussed alter)
Firstfunc
;subroutine
Add r0,r0,r1
;Add r0+r1r0
Mov pc, lr
Return from subroutine, to caller
end
;end of file

17. Current Program Status Register (CPSR)
Exercise 2 Fill in the shaded areas. Program counter PC =R15, #value = intermediate constant value
Address (H)
Comments
After instruction is run PC
PC (Hex) C
R0(Hex)
R1(Hex)
R2 (Hex)
All registers R0-R2 are rest to 0 here
Mov r1,#15
;r1=15 f
ffff ffff
Mov r2,#0xffffffff
;r2=#0xffffffff
;i.e. r2= -1
ADDs r0,r1,r2
;r0=r1+r2
ADCs r0,r1,r2
;r0=r1+r2+C
SUBs r0,r1,r2
;r0=r1-r2
SBCs r0,r1,r2
;r0=r1-r2+C-1

18. Current Program Status Register (CPSR)
Exercise 3 Fill in the shaded areas. Program counter PC =R15, #value = intermediate constant value
Address (H)
Comments
After instruction is run PC
R0(Hex)
R1(Hex)
R2(Hex) NZ
At the beginning H H H 00
ANDs r0,r1,r2
;r0=r1 and r2 (bit by bit )
ORRs r0,r1,r2
;r0=r1 or r2
EORs r0,r1,r2
;r0=r1 xor r2
BICs r0,r1,r2
;r0=r1 and (not r2)
R1=55H= B
R2=61H= B
9EH= B

19. Current Program Status Register (CPSR)
Exercise 4 Fill in the shaded areas. Program counter PC =R15, #value = intermediate constant value
Address (H)
Comments
After instruction is run PC
R0(Hex)
R1(Hex)
R2(Hex)
At the beginning H H
MOV r2,#12
;r2=#12
MOV r0,r2
;r0=r2
MVN r1,r2
;r1= not r2
Hint : decimal 12=1100(Binary)=C (HEX)

20. Exercise 5 , Fill in the shaded areas.
Address (H)
Comments
After instruction is run PC
NZCV (binary)
R1 (Hex)
R2 (Hex)
All registers R0-R2=0 and NZCV=0000 (binary), here
Mov r1,#0x11
;r1=
Mov r2,#0x23
;r2=
CMP r1, r2
; set cc on r1 - r2 (compare)
Mov r1,r2
; r1<=r2
N = 1 if MSB of (r1 - r2) is '1‘ (MSB of result is sign bit, 1 = negative)
Z=1 when the result is zero
C=1 when a binary addition generates a carry out; (for 32-bit integer 2’s comp. addition, C is ignored, see appendix.)
V=1 (when result of add, subtract, or compare is >= 231, or < –231.). I.e.
if two -ve numbers are added, the result is +ve (underflow).
if two +ve numbers are added, the result is -ve (overflow).
If the two numbers are of different signs, no overflow/underflow.

21. Exercise 6 Fill in the shaded areas.
TST updates the N and Z flags according to the result, It
does not affect the C or V flags.
Exercise 6 Fill in the shaded areas.
Address (H)
Comments
After instruction is run PC
NZCV (binary)
R1 (Hex)
R2 (Hex)
All registers R0-R2=0 and NZCV=0000, here
Mov r1,#15
;r1=15 decimal
Mov r2,#0x240
;r2=0xF0 (0xf is 240 in decimal)
TST r1,r2
; set cc on r1 AND r2 (logical AND operation test bits)
TEQ r1,r2
; set cc on r1 xor r2 (test equivalent)
Convert hex to decimal :
And
Result
Xor
Result