1. Instruction sets : Addressing modes and Formats
Unit 2
Instruction sets : Addressing modes and Formats

2. Topics to be covered Addressing Modes X86 And ARM Addressing Modes
Instruction Formats
X86 And ARM Instruction Formats
Assembly Language

3. 11.1 Addressing Modes Addressing Modes Immediate Direct Indirect
Register
Register indirect
Displacement
Stack

4. Addressing Modes
X86 Addressing Modes
ARM Addressing Modes

5. x86 Addressing Mode Calculation

7. ARM Addressing modes Load /Store addressing:
This instruction reference memory
It is done with the help of base register plus offset.
3 alternatives with respect to indexing
OFFSET
PREINDEX
POSTINDEX

8. An offset value is added to or subtracted from the value in the base register to from the memory
This is the store byte instruction.
In this case base add in r1 and displacement is immediate value 12 the resulting add is location where least significant byte is stored.

9. Pre-index
Memory add is formed in the same way as for the offset address
The memory add is also written back to the register
The above example show this

10. Post index
An offset is added to or subtracted from the base register value and the result is written back to the base register.
this method with the assembly language instruction STRB r0, [r1], #12.

11. Data processing instruction addressing
Data processing instructions use either register addressing of a mixture of register and immediate addressing.
Branch instructions
It is immediate addressing
For calculation the value is shifted left 2 bits and the program counter is used for the address range.

12. Load and store multiple addressing
Load Multiple instructions load a subset (possibly all) of the general-purpose registers from memory.
Store Multiple instructions store a subset (possibly all) of the general-purpose registers to memory
Load and Store Multiple addressing modes produce a sequential range of memory addresses.
The lowest numbered register is stored at the lowest memory address and the highest numbered register at the highest memory address.

13. Four addressing modes are used increment after, increment before, decrement after, and decrement before.
A base register specifies a main memory address where register values are stored in or loaded from in ascending (increment) or descending (decrement) word locations.
Incrementing or decrementing starts either before or after the first memory access.
These instructions are useful for block loads or stores, stack operations, and procedure exit sequences.

15. 11.3 INSTRUCTION FORMATS Instruction Length
This decision affects, and is affected by, memory size, memory organization, bus structure, processor complexity, and processor speed.
This decision determines the richness and flexibility of the machine as seen by the assembly-language programmer.
Programmers want more op-codes, more operands, more addressing modes, and greater address range
More op-codes & more operands make easier for the programmer, because shorter programs can be written to accomplish given tasks.

16. Similarly, more addressing modes give the programmer greater flexibility in implementing certain functions.
the increase in main memory size and the increasing use of virtual memory, programmers want to be able to address larger memory ranges
All of these things (op-codes, operands, addressing modes, address range) require bits and push in the direction of longer instruction lengths
Either the instruction length should be equal to the memory- length (in a bus system, data-bus length)
One solution is to use cache memory another is to use shorter instructions. Thus, 16-bit instructions can be fetched at twice the rate of 32-bit instructions but probably can be executed less than twice as rapidly.

17. Allocation of Bits Number of addressing modes
implicit (single AM)and explicit (One or more AM)
Number of operands
Register versus memory
why register and why memory?
Number of register sets
Address range
depends on address bites
Address granularity

18. Instruction Designs : PDP-8
The PDP-8 uses 12-bit instructions and operates on 12-bit words.
There are a 3-bit opcode and three types of instructions.
Each memory reference consists of 7 bits plus two 1-bit modifiers
For op-codes 0 through 5, the format is a single-address memory reference instruction including a page bit and an indirect bit.

19. PDP-8 Instruction Format

20. Memory Reference Instruction
op - the op-code. i - the indirect bit (0 = direct, 1 = indirect). z - the page bit (0 = page zero, 1 = current page). addr - the word in page.

21. Input/output instruction
The IOT instruction has the following form: _ _ _ _ _ _ _ _ _ _ _ _ |1|1|0|_|_|_|_|_|_|_|_|_| | | | | | | device | op |
|1|1|0|_|_|_|_|_|_|_|_|_| | | KSF - keyboard skip if flag | | KCC - keyboard clear flag | | KRS - keyboard read static

22. The basic op-codes for memory reference instruction
000 - AND - and operand with AC ADD - add operand to (a 13 bit value) ISZ - increment operand and skip if result is zero DCA - deposit AC in memory and clear JMS - jump to subroutine JMP - jump IOT - input/output transfer OPR – micro-coded operations

23. PDP-10 Orthogonality: Completeness: Direct addressing
The PDP-10 has a 36-bit word length and a 36-bit instruction length
The opcode occupies 9 bits, allowing up to 512 operations.
A 36-bit instruction length is true luxury. There is no need to do clever things to get more opcodes; a 9-bit opcode field is more than adequate.

24. PDP-10 Instruction Format

25. PDP-11 Instruction Format

26. PDP-11
PDP-11 was designed to provide a powerful and flexible instruction set within the constraints of a 16-bit minicomputer
Thirteen different formats are used, encompassing zero-, one-, and two-address instruction types.
The PDP-11 instruction set and addressing capability are complex.
This increases both hardware cost and programming complexity.
The advantage is that more efficient or compact programs can be developed.

27. X86 INSTRUCTION FORMATS

28. Instruction prefixes:
The instruction prefix, if present, consists of the LOCK prefix or one of the repeat prefixes.
The LOCK prefix is used to ensure exclusive use of shared memory in multiprocessor environments.
The repeat prefixes specify repeated operation of a string, which enables the x86 to process strings much faster than with a regular software loop.
There are five different repeat prefixes: REP, REPE, REPZ, REPNE, and REPNZ.
Segment override:
Explicitly specifies which segment register an instruction should use.

29. Operand size: Address size: Opcode:
An instruction has a default operand size of 16 or 32 bits
the operand prefix switches between 32-bit and 16-bit operands.
Address size:
The processor can address memory using either 16- or 32-bit addresses.
The address size determines the displacement size in instructions and the size of address offsets generated during effective address calculation
Opcode:
The opcode field is 1, 2, or 3 bytes in length. The opcode may also include bits.

30. Mod R/m:
This byte, and the next, provide addressing information.
The Mod R/m byte specifies whether an operand is in a register or in memory;
if it is in memory, then fields within the byte specify the addressing mode to be used.
SIB:
The SIB byte consists of three fields:
The Scale field (2 bits) specifies the scale factor for scaled indexing;
The Index field (3 bits) specifies the index register;
The Base field (3 bits) specifies the base register.
Displacement:
When the addressing-mode specified indicates that a displacement is used, an 8-, 16-, or 32-bit signed integer displacement field is
added.
Immediate:
Provides the value of an 8-, 16-, or 32-bit operand.

31. ARM Instruction Formats

34. All instructions in the ARM architecture are 32 bits long and follow a regular format.
The first four bits of an instruction are the condition code.
The next three bits specify the general type of instruction.
The next five bits constitute an opcode and/or modifier bits for the operation.
The remaining 20 bits are for operand addressing.

35. THUMB INSTRUCTION SET
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
Thumb is designed to increase the performance of ARM implementations that use a 16-bit.
The Thumb instruction set contains a subset of the ARM 32-bit instruction set recoded into 16-bit instructions.
The savings is achieved in the following way:-
1. Thumb instructions are unconditional, so the condition code field is not used. Also, all Thumb arithmetic and logic instructions update the condition flags, so that the update-flag bit is not needed. Savings: 5 bits.
2. Thumb has only a subset of the operations in the full instruction set and uses only a 2-bit op-code field, plus a 3-bit type field. Savings: 2 bits.
3. The remaining savings of 9 bits comes from reductions in the operand specifications. For example, Thumb instructions reference only registers r0 through r7, so only 3 bits are required for register references, rather than 4 bits. Immediate values do not include a 4-bit rotate field.

37. ASSEMBLY LANGUAGE Consider the simple BASIC statement N = I + J + K.
Suppose we wished to program this statement in machine language and to initialize I, J, and K to 2, 3, and 4, respectively.
Load the contents of location 201 into the AC.
Add the contents of location 202 to the AC.
Add the contents of location 203 to the AC.
Store the contents of the AC in location 204.

39. With this last refinement, we have an assembly language.
Programs written in assembly language (assembly programs) are translated into machine language by an assembler.
This program must not only do the symbolic translation discussed earlier but also assign some form of memory addresses to symbolic addresses.