1. ARM Intro

2. ARM The Company
Advanced Risc Machines Founded November 1990 : Acorn Computers & Apple
Designs the ARM range of RISC processor cores
Licenses designs ARM does not fabricate chips

3. ARM Users

4. ARM Types Confusing naming Modern processors "Cortex"
Early processors named ARM____
Architectures numbered ARMv___
Ex: ARM11 is based on ARMv6
Modern processors "Cortex"
Current architecture v8
32 and 64 bit flavors

5. ARM Types
Current ARM cores : Cortex

6. ARM 32bit Block Diagram
Load/Store Architecture
32 bit word size

7. OS & Memory 32 bit memory map: 232 = 4GB of addresses
OS generally reserves memory for devices and critical OS code
RAM 2 GB
0xFFFFFFFF 0x
Mapped IO Devices 1 GB
0x7FFFFFFF 0x
RAM/ROM/IO ~1 GB
0x3FFFFFFF 0x
Boot ROM 64 KB
0x000FFFFF 0x

8. Registers 16 application registers available 15 read/write
3 reserved
1 status register

9. Registers
Extra registers used by other processor levels:

10. Basic Code
A simple program: @ Start line comment /* … */ Multiline comment

11. Basic Code
A simple program: _start: Label indicating entry point

12. Basic Code
A simple program: MOV rd, #___ put constant in rd (rd  #) MOV rd, rs copy rs to rd (rd  rs)

13. SWI SWI : SoftWare Interrupt "Operating System please do something"
AKA syscall
@Syscall in ARMSim
@ooops, I need OS to do something for me....
MOV r0, #code @load code for function in r0
SWI 0x @cause SoftWare Interrupt

14. Exit
0x11 = Halt execution
m_UserGuide4Plus.pdf
Page 20

15. ARM Sim
Simulates basics of running code on ARM processor

16. Enabling SWI Current Version: Old Version:
FilePreferences Plugins Check LegacySWIInstructions
Old Version:
FilePreferences Plugins Check SWIInstructions

17. ADD Instruction
ADD rd, rn, rm rd  rn + rm ADD rd, rn, #__ rd  rn + # Constant MUST be second

18. Subtract Instructions
SUB rd, rn, rm rd  rn - rm SUB rd, rn, #__ rd  rn - # Constant MUST be second

19. Subtract Instructions
SUB rd, rn, rm rd  rn - rm SUB rd, rn, #__ rd  rn - # Constant MUST be second Reverse Subtract: RSB rd, rn, rm rd  rm - rn RSB rd, rn, #__ rd  # - rn Reverses order of source operands

20. Instruction
An instruction: E

21. Decoding

22. Decoding
E Condition code = Operator1 = 000 Operator = 0

23. Decoding
E Condition code = Operator1 = 000 Operator = 0

24. Decoding
E Operator = 0 Operator1 = Operator2 = 0000

25. Decoding
E Operator = imm5 = Operator2 = 00

26. Decoding
E Rn (start) = 1 Rd (destination) = 3 Rm (subtracted) = 2

27. Instruction #2
Instruction # E A E

28. Decoding #2
E A E Condition code = Operator1 = 001 Operator = 1

29. Decoding #2
E A E Operator = 1 Operator1 = Operator2 = 0011

30. Decoding #2
E A E Operator = imm5 = Operator2 = 01

31. Decoding #2
E A E Rd (destination register) = imm12 = = 3634????

32. Rotate With Wrap
Right rotations with wrapping: Original  Original  Original  Original 

33. Immediate Encoding 12 bit immediate stored as 8 bit immediate
4 bit rotation amount x2 places to right with wrap E
Rotation = 1110 = x 2 = 28 Immed_8 =

34. Immediate Encoding
Rotation = 1110 = x 2 = 28 Immed_8 =
= 800

35. Immediate Issues
Not all values can be encoded as 8 significant bits shifted:

36. MVN
Move NOT – puts inverse bit pattern in register (flip source bits) MVN rd, rs copy opposite of rs to rd(rd  𝑟𝑠 ) MVN rd, #___ copy opposite of constant in rd (rd  # )

37. Pseudo Instructions
Pseudo Intruction: Supported by assembler, not be hardware

38. Pseudo Instructions
Pseudo Intruction: Supported by assembler, not be hardware

39. Pseudo Instructions
Pseudo Intruction: Supported by assembler, not be hardware Replaced with other instruction(s)