Giuliana Rizzo INFN and University, Pisa on behalf of SVT-SuperB group

Giuliana Rizzo INFN and University, Pisa on behalf of SVT-SuperB group
Silicon Vertex Tracker R&D towards the Technical Design Report Giuliana Rizzo INFN and University, Pisa on behalf of SVT-SuperB group The SVT in the CDR From CDR to TDR Main Goals of the R&D SuperB Detector R&D Workshop SLAC February G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

SuperB Vertex Detector Design Issues
SuperB SVT concept based on Babar SVT with modifications required to operate at a L=1036 cm-2 s-1 and with the reduced SuperB boost Main Issues Impact on Vertex Separation significance Smaller beam energy asymmetry 7+4 GeV  bg=0.28 SuperB (bg=0.55 BaBar) Reduces average vertex separation by ~ 2 w.r.t. BaBar: <Dz>~ (bg)Y(4S) ct ~130 SuperB Time dependent analyses require <Dz>/s(Dz) > ~2 (keep BaBar as target): Radius of beam pipe and first SVT layer need to be reduced: Vertex resolution dominated by first layers: the closer to the IP the better Improves BaBar SuperB boost > Detector segmentation to reduce occupancy to acceptable level (<10%) > Radiation hardness Dose ~ 1 Mrad/yr Equivalent fluence ~ 1012 n/cm2/yr Machine backgrounds with high luminosity/ “squeezed” bunches/low currents: Present etimate (simulation) of total background rate at SVT inner layer location ~ 5 MHz/cm2 G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

SuperB Workshop - SLAC Feb. 14, 2008
SuperB SVT Geometry 40 cm 30 cm 20 cm Layer0 Layer Radius cm cm cm cm to 12.7 cm to 14.6 cm Baseline: use an SVT similar to the BaBar one adding a Layer0 Cannot reuse BaBar SVT because of radiation damage Fast Simulation indicates target performance achievable with: b.p. inner radius: 1.0cm, Layer0 radius: cm b.p.+Layer0 material: <0.5%-0.5% X0 Dt resolution (a Dz) BaBar Improves A beam pipe with r ~ 1 cm highly desirable, but needs to be cooled. Study is in progress to keep total thickness low ~ 0.5 % of X0 G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

Layer 0 Options The BaBar SVT technology is adequate for R > 3cm: use design similar to BaBar SVT Layer0 is subject to large backround and needs to be extremely thin: > 5MHz/cm2, 1MRad/yr, < 0.5%X0 Striplets option: mature technology, not so robust against background. Marginal with background rate higher than ~ 5 MHz/cm2 Moderate R&D needed on module interconnection/mechanics/FE chip (FSSR2) CMOS MAPS option new & challenging technology: can provide the required thickness existing devices are too slow Extensive R&D ongoing (SLIM5-Collaboration) on 3-well devices 50x50um2 Hybrid Pixel Option: tends to be too thick. An example: Alice hybrid pixel module ~ 1% X0 Possible material reduction with the latest technology improvements Viable option, although marginal G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

SVT Activities from CDR to TDR
Bergamo, Bologna, Pavia, Pisa, Torino, Trieste (SLIM5-Collaboration) Need more groups! Milano … Background studies E. Paoloni Optimize detector space-time granularity and verify radiation levels Check radiation level also outside the active area (HDI location) Simulation studies N. Neri Strongly connected with machine design and backgrounds simulation Optimize detector geometry and granularity Strong ongoing R&D MAPS sensor chip development: Fast readout architecture A. Gabrielli Pixel cell optimization V. Re Radiation hardness Mechanical issues: F. Bosi sensor thinning, module design, low mass cooling striplets module Test Beam foreseen in Sep ‘08 S. Bettarini/M.Bomben Prototype MAPS module + striplets Talks in SVT parallel sessions indicated Explore alternative technological solution for Layer 0 Hybrid Pixel Option: need to investigate possible material/pitch reduction to reach the SuperB requirements Multichip pixel module design and options for data transmission (data driven vs triggered options) need to be studied Design of the Layers 1-5: investigate existing front-end chip, module design… Integration Issues Need to start soon G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

SuperB Low currents (2A): Beam-gas are not a problem (similar to BaBar) SR fan can be shielded High luminosity  dominated by QED cross section IR design Rate reduced to 5 MHz/cm2 at first SVT layer since e+/e- have low energy and loop in the 1.5T B field. Rate reduced to ~ 100 SVT Layer 0 location with present IR design and proper shielding to prevent the produced shower from reaching the detector Rate (Mhz/cm2) G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008 Radius (cm)

Touschek Background Intrabeam scattering produces Touschek particles all along the ring, depending on emittance and bunch volume Beam optics and collimator setting essential in controlling this background Two-step simulation: estimate primary Touschek particles hitting the B.P. in the I.R. with dedicated code track the particles in the detector volume with G4 simulation New lattice and collimators VERY effective Not an issue anymore Need to be carefully verified with final design G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

Radius, thickness, resolution
Technological solutions depend critically on L0 radius, thickness, resolution Fast simulation studies for various decays have been performed A full, more detailed reassessment is needed for the TDR. MAPS low mass solution would leave more flexibility for radius (ie background) and resolution Hybrid pixels will force to use the smallest radius and/or better resolution Striplets (same MAPS material) require larger radius, performance marginal Dt resolution in Bpp decays vs L0 X0(%) 10mm resolution 5mm resolution BaBar beam pipe material: 0.4% X0 b. p. inner R 1cm, o.r. 1.1 cm layer0 radii = 1.2, 1.5, 1.7 cm material for L0 = [ ] % X0 hit resolution = [5-15] mm MAPS MAPS G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

CMOS Monolithic Active Pixels
Developed for imaging applications Several reasons make them very appealing as tracking devices : detector & readout on the same substrate wafer can be thinned down to few tens of mm radiation hardness (oxide ~nm thick) high functional density and versatility low power consumption and fabrication costs Principle of operation The undepleted epitaxial layer acts as a potential well for electrons Signal (~1000 e-) collected through diffusion by the n-well contact Charge-to-voltage conversion provided by the sensor capacitance  small collecting electrode Simple in-pixel readout (additionals nwells for PMOS not allowed in standard MAPS design!)  sequential readout PMOS “Competitive” nwells for PMOS not allowed in standard MAPS design! G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

Deep NWell MAPS design New approach in CMOS MAPS design to improve the readout speed potential: APSEL chip series SLIM5 Collaboration - INFN & Italian University Full in-pixel signal processing realized exploiting triple well CMOS process Deep nwell (DNW) as collecting electrode Gain independent of the sensor capacitance collecting electrode can be extended Area of the “competitive” nwells inside the pixel kept to a minimum:, they steel signal to the main DNW electrode. Fill factor = DNW/total n-well area ~90% in the prototype test structures Pixel structure compatible with data sparsification architecture to improve readout speed. PRE SHAPER DISC LATCH competitive nwell Deep nwell Proof of principle with the first prototypes realized in 130 nm triple well CMOS process (STMicrolectronics) G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

Submitted DNW MAPS Chips 130 nm ST
IC group contribution: Pavia (PV)-Bergamo(BG) analog front-end Pisa(PI)-PV-BG in pixel digital logic Bologna-PI digital readout architecture Submitted DNW MAPS Chips 130 nm ST Sub. 8/2006 Sub. 9/2006 Sub. 12/2004 Sub. 8/2005 APSEL2M Cure thr disp. and induction APSEL2T Accessible pixel Study pix resp. APSEL2_90 TEST_STRUCT ST 130 Process characterization APSEL0 Preamplifier characteriz. APSEL1 Improved F-E 8x8 Matrix ST 90nm characterization Sub. 11/2006 Sub. 5/2007 Sub. 7/2007 Sub. 7/2007 APSEL2D APSEL2_CT APSEL3D APSEL3_T1, T2 8x32 matrix. Shielded pixel Data Driven sparsified readout Test chips to optimize pixel and FE layout Test digital RO architecture Test chips for shield, xtalk G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

Fast Readout Architecture for MAPS
Data-driven readout architecture with sparsification and timestamp information under development. In the active sensor area we need to minimize: the logical blocks with PMOS to minimize the competitive nwell area and preserve the collection efficiency of the DNW sensor. digital lines for point to point connections to allow scalability of the architecture with matrix dimensions and to reduce cross talk with the sensor underneath. MP 4x4 pixels Matrix subdivided in MacroPixel (MP=4x4) with point to point connection to the periphery readout logic: Register hit MP & store timestamp Enable MP readout Receive, sparsify, format data to output bus Data lines in common 2 MP private lines Column enable lines in common Periphery readout logic APSEL3D: 256 pixels under test APSEL4D: 4k pixels Sub. Nov. 2007 Data out bus G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008 50x50 um pitch

3x3 matrix, full analog output
APSEL2 chips results 3x3 matrix, full analog output 90Sr electrons Landau mV S/N=14 Cluster signal (mV) 50 mm pixel pitch Cluster Multiplicity 1 2 Noise events properly normalized Hit pixels in 3x3 matrix apsel2T chip 5: gain 578 mV/fC Noise ENC = 50 e- Indications of small cluster size (1-2 pixels) Cluster Signal for MIP (Landau MPV) 700 e- S/N = 14 Threshold dispersion = 100 e- (Noise x2 still high!) Digital crosstalk effects present Cluster seed G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

Analog routing (local) Digital routing (local/global)
From APSEL2 to APSEL3 APSEL2 issues APSEL3D Digital lines shielding Cross talk between digital lines and substrate Requires aF level parasitic extraction to be modeled Relatively small S/N ratio (about 15) Especially important if pixel eff. not 100% Power dissipation 60 mW/pixel Creates significant system issues M1 M2 M3 M5 M6 M4 Analog routing (local) Digital routing (local/global) Shield (VDD/GND) APSEL3 Redesigned front-end/sensor Optimize FE Noise/Power: Reduce sensor capacitance (from 500 fF to ~300 fF) keeping the same collecting electrode area reduce DNW sensor/analog FE area (DNW large C) Add standard NWELL area (lower C) to collecting electrode. New design of the analog part Optimize sensor geometry for charge collection efficiency using fast simulation developed: Locate low efficiency region inside pixel cell Add ad hoc “satellite” collecting electrodes APSEL3 Power=30 mW/pixel: Performance APSEL3 expected performance Expand this slide? Simulation Result on shiled FE Version Geom. ENC (PLS) S/N APSEL2 data A 50 e- 88.7% 14 APSEL3 Transc. B 41 e- 93.6% 99.4% 16 18 Curr. Mirror 31 e- 98.6% 99.9% 22 24 G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

APSEL3 chips now under test
APSEL3T1 Preliminary Very preliminary! S/N = 20 for MIP from Sr90 Absolute calibration of noise and gain still under way 90Sr electrons Landau mV S/N=20 Cluster signal (mV) Noise events properly normalized First test on APSEL3D (256 pixels): readout works as expected…with some bugs found! Noise scan (hit rate vs discriminator threshold) to measure noise and threshold dispersion. APSEL3D Preliminary Occupancy Metal shield effective to reduce crosstalk effects due to digital lines crossing the pixel. This source is now at the level of the pixel noise… But some digital crosstalk still present in the APSEL3 series…different source? Power distribution problem? G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008 Vth (DAC)

CMOS MAPS R&D goals TDR time scale: build a prototype multichip MAPS module suitable for application in Layer 0. Demonstrate the ability to build a working detector with this technology. Present R&D on DNW MAPS very encouraging Need to demonstrate fast readout architecture implementation is possible with this technology (R=5MHz/cm2, continous beam structure) Crosstalk due to digital line crossing the pixel seems cured but still some effects are present (power distribution? ) Scalability of the readout architecture to large matrix (Area ~1 cm2) 256 pixel matrix produced: test started. - 4k pixel matrix in production Nov. ’07 Issues for larger matrix: power distribution, output rate. efficiency of the readout Explore alternative architecture: data driven vs triggered architecture. Pixel cell optimization to improve S/N, charge collection efficiency, power dissipation. S/N = 1524, Power=30 mW/ch in chips just received Evaluate different technology (IBM 130 nm triple well) Radiation tolerance: tests performed on CMOS MAPS from other groups indicate adequate rad. hardness for SuperB. Some effects are design/process dependent needs to be investigated on our DNW MAPS. Irradiation program just started Optimize pixel cell for radiation hardness G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

Mechanics & Module design R&D
MAPS module proposed (AlN support + minichannel with cold liquid) Two MAPS layers (up/down) placed on the mechanical support forming a ladder. Each chip: 12.8mm x 12.8mm. Total Layer0 thickness: 0.5 % X0 0.1 % (Si) % (Supp+Cooling) % (bus/Cu) MAPS power dissipation is large (in the active area!) Power = 50 μW/cell = 2 W/cm2 Power dissipation drives the mechanical problem FEA for MAPS module proposed indicates power evacuation possible with a support/cooling thickness ~ 0.3% X0: Extensive R&D activity on microcooling See F. Bosi’s talk at the SVT parallel session. Need to demonstrate feasibilty with meas. on mechanical prototype Thermoidraulic Testbench in prep. for accurate thermic measurements Mechanincal activity also to optimize the design of the striplets option. G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

Explore more advanced technological solutions
Improvements w.r.t explored Layer 0 solutions could be achieved with: Vertical Integration of thin chips: high resistivity pixel sensor + CMOS readout chip in less than 100 um. Integration of microcooling techniques on Si chips themselves Hopefully start R&D by the end of 2008 (PRIN Project submitted, pending approval …) These technologies might not be ready when the SuperB construction starts but could be mature for an upgrade of Layer 0 (we need to design an interaction region with easier access & replacement). G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

Test Beam in Sept. 2008 Test DNW MAPS on beam Measure rate capability, efficiency, resolution Test Associative Memories - based LVL1 trigger Focus on system issues for SuperB Layer 0 application Striplets with FSSR2 chip 32x128 MAPS matrix with data driven architecture beam T-1,2,3,4 :reference telescope modules DSSD 300 mm thick, 2x2 cm2 50 mm r.o. pitch (3 chip FSSR2/side) S-1,2,3 scintillator Striplets-1,2: (1.29x7.0 cm2 ) DSSD 200 mm thick (45o) 25 p-side, 50 n-side mm pitch 50 mm r.o. pitch (chip FSSR2) MAPS-1,2 : MAPS (several mm2) 50x50 mm2 (5080 mm-thick) S1 S2 S3 T-2,1 T-4,3 Striplets-1 Striplets-2 MAPS-1 MAPS-2 G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

Conclusions We have an SVT detector concept based on Babar with modifications required to operate at a L=1036 cm-2 s-1 and with the reduced SuperB boost: BaBar SVT + Layer 0 Still, a significant amount of work is needed to turn this concept into a full detector design and write a Technical Design Report: Strong ongoing R&D on technology development for Layer 0 (MAPS, low mass cooling…) Physics studies to optimize overall detector geometry Background studies to optimize detector space-time granularity and verify radiation levels Detector physics-engineering studies to produce a sound subsystem design Activities in some areas not yet covered but need to start soon More details on where we stand in this process and plans for future developments will be presented in the SVT parallel session (Friday morning). G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

backup G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

Beam pipe Beampipe X0 Gold foil 4 mm % Berillium 600 mm % Water 300 mm % Ni coating 7 mm % 1.0 cm inner radius Be inner wall ≈ 4um inside Au coating 8 water cooled channels (0.3mm thick) Power ≈ 1kW Peek outer wall Outer radius ≈ 1.2cm Thermal simulation shows max T ≈ 55°C Issues Connection to rest of b.p. Be corrosion Outer wall may be required to be thermally conductive to cool pixels Total % backup G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

APSEL3D 256 pixel matrix with sparsified readout and timestamp - submitted 7/2007 Innovative mixed mode design Pixel cell with full custom design and layout Sparsifying logic synthetized in std-cell from VHDL model Essential for large matrix design with complex logic Encouraging results on hit efficiency from VHDL simulation: e > 99% with hit rate up to several hundreds MHz/cm2 (small matrix/preliminary study) 256 pixels - 50 mm pixel pitch The periphery contains readout architecture AND a digital emulator of the matrix built with standard cell. This could be used to test the readout independently of the MAPS sensor matrix. G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

APSEL2 8x8 matrix: digital output 8x8 matrix digital output
Noise scan: hit rate vs discriminator threshold Vthr Noise 8x8 matrix digital output Sequential readout Vth (mV) Threshold dispersion ~ 100 e- 90Sr electrons: single pixel spectrum APSEL2M chip 2: gain 530 mV.fC Spectrum from analog output Differential spectrum from digital output Noise (mV) Average Noise ENC = 50 e- G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

An example of sensor optimization
With old sensor geometry (left) Efficiency ~ 93.5% from simulation (pixel 250 e- = 5xNoise) Inefficient regions shown with dots (pixel signal < 250 e-) Cell optimized with satellite nwells (right) Efficiency ~ 99.5% 3x3 MATRIX sensor optimized 3x3 MATRIX old sensor geom Satellite nwells connected to central DNW elect Competitive Nwells To be updated with new numbers on efficiency and plot apsel3T DNW collecting electrode G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

MAPS Radiation Hardness
Expected Layer0: Dose = 6Mrad/yr Equivalent fluence = 6x1012 neq/cm2/yr x5 safety factor included CMOS redout electronics (deep submicron) rad hard MAPS sensor - Radiation damage affects S/N Non-ionizing radiation: bulk damage cause charge collection reduction, due to lower minority carrier lifetime (trapping)  fluences ~ 1012 neq/cm2 affordable, 1013 neq/cm2 possible Ionizing radiation: noise increase, due to higher diode leakage current (surface damage)  OK up to 20 Mrad with low integration time (10 ms) or T operation < 0o C, or modified pixel design to improve it Results from standard nwell MAPS prototypes Irradiation test performed on several MAPS prototypes, with standard nwell sensor, indicate application for SuperB is viable. APSEL chips irradiation started …. G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

APSEL3 chips now under test
Very preliminary! S/N = 20 for MIP from Sr90 Absolute calibration of noise and gain still under way 90Sr electrons Landau mV S/N=20 Cluster signal (mV) Noise events properly normalized Preliminary Test on APSEL3D (256 pixels): Threshold dispersion reduced at the level of the pixel noise. Preliminary Threshold dispersion 11 mV Metal shield effective to reduce crosstalk effects due to digital lines crossing the pixel. This source is now at the level of the pixel noise… But some digital crosstalk still present in the APSEL3 serie…different source? Power distribution problem? Vth (mV) Average Noise 11 mV Noise (mV) G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

R&D Organization for SVT
Basic R&D for the SuperB SVT Layer0 (sensor & electronics) partly included in the SLIM5 project (supported by the INFN and the Italian Ministry for Education, University and Research). SLIM5 activities in 2007/2008 focused to build a prototype of a thin silicon tracker (MAPS and thin silicon striplets modules) with LV1 trigger capabilities (based on Associative Memories)  test beam in 2008. Some aspects of the Layer0 CDR design (system/mechanical aspects) are not covered by SLIM5 project: specific funding (2008) from INFN (CSN1) for SuperB detector. Italian Institutes already involved in SLIM5 confirmed their interest in the SVT R&D for the SuperB project: Pisa, Pavia, Bergamo,Trieste, Torino, Bologna Milano just joined the SVT SuperB effort. Other groups (Roma III, Perugia), already active in MAPS R&D for ILC, expressed their interest for our activities (important synergy to exploit) G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

SLIM5-Silicon detectors with Low Interactions with Material
Basic R&D for Layer0 (CMOS MAPS and thin strips) started in 2004 within the SLIM5 Collaboration. Several Italian Institutions involved in the project: BO, PI (coordination), PV-BG, TO, TN, TS. R&D project supported by the INFN and the Italian Ministry for Education, University and Research. SLIM5 Purpose: develop technology for thin silicon tracker systems (sensor/ readout/ support structure/ cooling) crucial to reduce multiple scattering effects for future collider experiments (SuperB, ILC) Realize a demonstration thin silicon tracker with LVL1 trigger capabilities: CMOS monolithic active pixels Thin strip detectors on high resistivity silicon Associative memory system for track trigger Low mass mechanical support and services Test beam foreseen in to measure rate capability, efficiency,resolution SLIM5 Project G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

SLIM5-Silicon detectors with Low Interactions with Material
G. Batignani1,2, S. Bettarini1,2, F. Bosi1,2, G. Calderini1,2, R. Cenci1,2, M. Dell’Orso1,2, F. Forti1,2, P.Giannetti1,2 , M. A. Giorgi1,2, A. Lusiani2,3, G. Marchiori1,2, F. Morsani2, N. Neri2, E. Paoloni1,2, G. Rizzo1,2 , J. Walsh2 C. Andreoli4,5, E. Pozzati4,5,L. Ratti4,5, V. Speziali4,5, M. Manghisoni5,6, V. Re5,6, G. Traversi5,6, L.Gaioni4,5 L. Bosisio7, G. Giacomini7, L. Lanceri7, I. Rachevskaia7, L. Vitale7, M. Bruschi8, B. Giacobbe8,A. Gabrielli8, N. Semprini8, R. Spighi8, M. Villa8, A. Zoccoli8, D. Gamba9, G. Giraudo9, P. Mereu9, G.F. Dalla Betta10 , G. Soncini10 , G. Fontana10 , L. Pancheri10 , G. Verzellesi11 1Università degli Studi di Pisa, 2INFN Pisa, 3Scuola Normale Superiore di Pisa, 4Università degli Studi di Pavia, 5INFN Pavia, 6Università degli Studi di Bergamo, 7INFN Trieste and Università degli Studi di Trieste 8INFN Bologna and Università degli Studi di Bologna 9INFN Torino and Università degli Studi di Torino 10Università degli Studi di Trento and INFN Padova 11Università degli Studi di Modena e Reggio Emilia and INFN Padova G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

Main Activities/Interests of the groups
Pisa MAPS (sensor optimization, test with particles, readout architecture, radiation damage) Light Mechanics & Cooling for striplets and MAPS modules Testbeam organization LV1 trigger with Associative Memories Pavia/Bergamo Front-end for MAPS & striplets Torino Mechanics Trieste Striplets (Sensor-FSSR2 hybrids-interconnections-beam telescope) Bologna DAQ for testbeam, MAPS readout architecture Milano MAPS development and mechanics G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

Module Layer0 (striplets): 3D-view
Carbon-Kevlar ribs End piece Striplets Si detector (fanout cut-away) Buttons (coupling HDI to flanges) Upilex fanout Hybrids chip G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

Layer0 striplets R&D issues
Technology for Layer0 striplets design well estabilshed Double sided Si strip detector 200 mm thick Existent readout chip (FSSR2 - BteV) meets the requirements for striplets readout with good S/N ~ 25. Readout speed and efficiency not an issue with the expected background rate (safety factor x5 included) 6% occupancy in 132 ns time window. Total thickness 0.45% X0 = (0.2 % (Si) % (Support) % Multiflex) Possible reduction in material ( 0.35% X0) with R&D on interconnections between Si sensor and FEE: Interconnections critical: high number of readout chans/module (~3000). Multiple layers of Upilex with Cu/gold traces with microbonding (as in SVT) Kapton/Al microcables with Tape Automated Bonding (as in ALICE experiment) Conceptual design module “flat” Readout Right Readout Left z HDI Si detector 12.9x97.0 mm2 1st fanout, 2nd fanout G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

Layer0 MAPS Module MAPS power dissipation is large (in the active area!) Power = 50 μW/cell = 2 W/cm2 Power dissipation drives the mechanical problem MAPS module proposed in CDR (microchannel with cold liquid) Two MAPS layers (up/down) placed on the mechanical support forming a ladder. Each chip: 12.8mm x 12.8mm. Total Layer0 thickness: 0.5 % X0 0.1 % (Si) % (Supp+Cooling) % (bus/Cu) Power: 2 W/cm2 on each Si surface Temperature (FEA results) Inlet cooling 10 °C DTmax= 8°C (H20 Flow=0.094 l / min2.5 m/sec) AlN-AlN Interface: 50 mm of Conductive Glue (4 watt/mK) Or other technique to reduce the junction thickness G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

Layer0 thickness Striplets module average thickness 0.46% X0 Silicon detector 200 mm Support structure ~ 100 mm Si eq. ~3 Upilex/Cu flex layers/module ~ 135 mm Si eq. Flex multilayer with Al could reduce by ~ 3 this contribution MAPS module average thickness 0.5% X0 Double layer MAPS 100 mm Support structure (AlN) + cooling ~ 300 mm Si eq. 2 Upilex/Cu flex layers/module ~ 90 mm Si eq. ALICE hybrid pixel average thickness 1 % X0 0.37 % X0 Si sensor+readout 0.1 % X0 support 0.3 % X0 cooling 0.17 % X0 Al multilayer bus G. Rizzo SuperB Workshop - SLAC Feb. 14, 2008

Giuliana Rizzo INFN and University, Pisa on behalf of SVT-SuperB group

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Giuliana Rizzo INFN and University, Pisa on behalf of SVT-SuperB group

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