1. Differencing Multistage Detector
ELEC423 Course Project
Gang Xu, Praful Kaul, Sridhar Rajagopal
April 28, 1999
Electrical and Computer Engineering Department,
Rice University, Houston,TX.

2. Description of the Chip -- MUDDY
8 synchronous mobile users
12-bit fixed point arithmetic
10-bit input/output interface
6100 transistors
34 pins
Cascade of 3 chips

3. Chip (Single Stage) Architecture
SHIFT A L U
RECODER
REG
(L+L’)A
Control
Logic
Internal signals
External signals

4. Chip Layout 2.4 mm Soft Decisions Recoding logic Cross-Correlation
12-bit ALU

5. System Timing
Load R
Final Output
1st Stage
2nd Stage
3rd Stage

6. IRSIM Simulation

7. Interference Cancellation

8. Fabrication and Testing Summary
Full functionality of all five chips
Test vectors are able to test all the possible states
8.5 MHz maximum clock rate
Cascade mode works, no glue logic necessary
Throughput of the system: 150kb/s/user
Delay of the system < 20s