1. Prototyping SoC-based Gate Drive Logic for Power Convertors by Generating code from Simulink models. Researchers Rounak Siddaiah, Graduate Student-University of Wisconsin-Milwaukee Rob Cuzner, Assistant Professor-University of Wisconsin-Milwaukee

2. 1.Introduction
In any Power Electronics Circuit Controlling switches are very crucial in how we control the output of the circuit.
This switching Sequence requirement varies depending on the total required output from the system.
Therefore Changing the Duty Cycle or Frequency of the switching sequence gives us control how much power is transmitted in the circuit from input to the output.
Our research focuses on how to practically implement and control the output in Real time.
We are using MATLAB and Simulink to model, simulate, and prototype control systems on Altera Cyclone V SoC devices, as shown in figure 2.
Generate C and HDL code to program control algorithms into an Altera Cyclone V SoC.
Control all the variables using Simulink or LABview dynamically.

3. Figure1: Workflow chart

4. 2.Model Based design workflow targeting Altera’s SOC Cyclone V
We model based on design workflow. This helps in rapid-Prototyping for faster development, as shown in figure1.
The control functions are partitioned between HPS and the FPGA fabric of the Embedded board.
The control in Simulink is programed using C(Autogen) directly from the Simulink model using Embedded and HDL coder.
There is also visualizing Feedback and data logging.
HDL code is generated targeting the FPGA fabric and for the AXI4 interface between the HPS and the FPGA IP core.
This is done with Altera Quartus QSYS environment and program the embedded board as shown In figure 4.
Generate the Software interface model where The HDL subsystem blocks are replaced with the AXI4 driver blocks in the Simulink model.
By automation we generate the c code of the driver block and run the c code on The ARM processor
Real time parameter tuning and verification in the external mode i.e. Processor in a loop.
This connected with Ethernet to the host computer for Dynamic tuning of the parameters.
Then finally deploy the code on to the Altera SOC FPGA. As shown in figure 3.

5. Figure2: Simulink Model

6. Figure3:Actual Implementation

7. 3.Theory of Operation of IP core
This IP core is designed to be connected to an embedded processor with an AXI4 interface. The processor acts as master, and the IP core acts as slave. By accessing the generated registers via the AXI4 interface, the processor can control the IP core, and read and write data from and to the IP core. As shown in figure 5.
This IP core also support the External Port interface. To connect the external ports to the FPGA external IO pins, add FPGA pin assignment constraints in the Altera Qsys environment.
Figure5: IP Core AXI4 interface.

8. Prototyping SoC-based Motor Controllers with MATLAB and Simulink
4.Software and Hardware Used
5. Conclusion
Simulink
Embedded coder
HDL coder
Quartus II(Includes QSYS)
Matlab
Altera SOC development board.
Simulink coder
Matlab coder
Adoptingon a single device, reduces system power, reduces cost and SoC devices to integrate processor and FPGA functions board size.
We can Control all the variables using Simulink or LABview dynamically.
Downloading programming to an Altera Cyclone V SoC Development Kit and test the Output signals.
6.References
Prototyping SoC-based Motor Controllers with MATLAB and Simulink
Ben Jeppesen, Altera Eric Cigan, MathWorks