1. Non Contiguous Memory Allocation
The disadvantages of contiguous allocation related to
Long search time of new memory blocks
Space waste due to fragmentation
Slow backing store management
are resolved using non-contiguous memory allocation.
One process – Many pieces of memory.
Paging is a memory-management scheme that permits the physical-address space of a process to be noncontiguous

2. Paging Basic Method
Page number
Frame number
Divide physical memory into fixed-sized blocks called frames
Size is power of 2, between 512 bytes and 16 Mbytes
Divide logical memory into blocks of same size called pages
Keep track of all free frames
To run a program of size N pages, need to find N free frames and load program
Set up a page table to translate logical to physical addresses
Backing store likewise split into pages
Physical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available
Still have internal fragmentation (no external fragmentation).

3. Paging Implementation
Address generated by CPU is divided into:
Page number (p) – used as an index into a page table which contains base address of each page in physical memory
Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit
For given logical address space 2m and page size 2n
The physical address is as follows: where f is a number of frame and d is the displacement within the frame.
Frame number
Offset in the frame F d

4. Paging Implementation
Paging itself is a form of dynamic relocation.
Every logical address is bound by the paging hardware to some physical address.
Using paging is similar to using a table of base (or relocation) registers, one for each frame of memory.

5. Paging example Paging example for a 32-byte memory with 4-byte pages.
Logical Addresses of the process
Paging example for a 32-byte memory with 4-byte pages.

6. Paging Fragmentation Calculating internal fragmentation
When we use a paging scheme, we have no external fragmentation:
Any free frame can be allocated to a process that needs it.
However, we may have some internal fragmentation.
Calculating internal fragmentation
Page size = 2,048 bytes Process size = 72,766 bytes
35 pages + 1,086 bytes
Internal fragmentation of 2, ,086 = 962 bytes
Worst case fragmentation = 1 frame for 1 byte
On average fragmentation = 1/2 frame size
So small frame sizes desirable?
But each page table entry takes memory to track
Page sizes growing over time
Solaris supports two page sizes – 8 KB and 4 MB
disk I/O is more efficient when the amount of data (page size) being transferred is larger

7. How is started the process paging
When a process arrives in the system to be executed, its size, expressed in pages, is examined.
Each page of the process needs one frame.
Thus, if the process requires n pages, at least n frames must be available in memory.
If n frames are available, they are allocated to this arriving process.
The first page of the process is loaded into one of the allocated frames, and the frame number is put in the page table for this process.
The next page is loaded into another frame, and its frame number is put into the page table, and so on
Figure Free frames (a) before allocation and after (b) allocation.

8. User memory - physical memory
An important aspect of paging is the clear separation between the user's view of memory and the actual physical memory.
The user program cannot access the other programs address space.
Can the user program change the mapping (page table)? Why?
The user program views that memory as one single contiguous space, containing only this one program.
In fact, the user program is scattered throughout physical memory, which also holds other programs.
The difference between the user's view of memory and the actual physical memory is reconciled by the address-translation hardware.
Natural Protection
This mapping is hidden from the user and is controlled by the operating system.
This is natural protection of process address space.
The user process by definition is unable to access memory it does not own.
It has no way of addressing memory outside of its page table, and the table includes only those pages that the process owns. X X

9. Frame Tables
Frame Table – keeps all memory frames status- allocation details of physical memory.
The frame table has one entry for each physical page frame and contains this information:
frame is allocated
to which process or processes it is allocated
frame is available
total frames

10. Page Tables
The operating system must be aware that user processes operate in user space.
The operating system maintains a copy of the page table for each process, just as it maintains a copy of the instruction counter and register contents.
This copy is used to translate logical addresses to physical addresses whenever the operating system must map a logical address to a physical address manually.
It is also used by the CPU dispatcher to define the hardware page table when a process is to be allocated the CPU
Paging therefore increases the context-switch time.

11. Process page tables Physical Memory PCB 1
PageTablePtr1
frame #7
frame #1
frame #8
frame #4
frame #5
frame #0
Most operating systems allocate a page table for each process.
A pointer to the page table is stored with the other register values (like the instruction counter) in the process control block.
When the dispatcher is told to start a process, it must reload the user registers and define the correct hardware page-table values from the stored user page table.
PCB 2
PageTablePtr2
frame #2
frame #3
frame #6
frame #9
frame #B
frame #A
3 references to the memory are needed to read the data:
Read PTB
Read frame number
Read the data itself

12. Hardware support
In the simplest case, the system page table is implemented as a set of dedicated registers with very high-speed logic to make the paging-address translation efficient.
The CPU dispatcher reloads these registers, just as it reloads the other registers
Instructions to load or modify the page-table registers are, of course, privileged, so that only the operating system can change the memory map.
Disadvantage: The use of registers for the page table is satisfactory if the page tables of processes are reasonably small (for example, 256 entries).
Modern computers allow the process page table to have 1 million entries.
Needs big hardware (not feasible)
Needs long context switch time
PageTablePtrA
frame #7
frame #1
frame #8
frame #4
frame #5
frame #0
PageTablePtrB
frame #2
frame #3
frame #6
frame #9
frame #B
frame #A
System page table on Hardware
256 entries

13. Hardware support only PTBR
For the machines with the large page tables (1 million entries) they are kept in memory.
and a Page-Table Base Register (PTBR) points to the page table.
Changing page tables requires changing only this one register, substantially reducing context-switch time.
Disadvantage: With this scheme, two memory accesses are needed to access a byte  
PageTablePtrA
frame #7
frame #1
frame #8
frame #4
frame #5
frame #0
PageTablePtrB
frame #2
frame #3
frame #6
frame #9
frame #B
frame #A
1 million entries
Page Table Base Register

14. PTBR twice access the memory
Disadvantage: With this scheme, two memory accesses are needed to access a byte
one for the page-table entry
one for the byte
PTBR
The standard solution to this problem is to use a special, small, fast lookup hardware cache, called a Translation Look-Aside Buffer (TLB).

15. Translation Look-Aside Buffer
PTBR
The TLB is associative, high-speed memory.
Each entry in the TLB consists of two parts: a key (or tag) and a value.
When the key is presented to TLB the corresponding value is returned

16. TLB as a fast cache of page table
The TLB is used with page tables in the following way
When a logical address is generated by the CPU, its page number is presented to the TLB.
If the page number is found, its frame number is immediately available and is used to access memory.
The whole task may take less than 10 percent longer than it would if an unmapped memory reference were used.
If the page number is not in the TLB (known as a TLB miss), a memory reference to the page table must be made.
When the frame number is obtained, we can use it to access memory
In addition, we add the page number and frame number to the TLB, so that they will be found quickly on the next reference.
PTBR
10% delay
Disadvantage: the hardware, however, is expensive. Typically, the number of entries in a TLB is small, often numbering between 64 and 1,024 (now 4096 – Wikipedia).

17. Process identification on TLB
Some TLBs store Address-Space Identifiers (ASIDs) in each TLB entry.
An ASID uniquely identifies each process and is used to provide address-space protection for that process.
When the TLB attempts to resolve virtual page numbers, it ensures that the ASID for the currently running process matches the ASID associated with the virtual page.
If the ASIDs do not match, the attempt is treated as a TLB miss.
PTBR
an ASID allows the TLB to contain entries for several different processes simultaneously.
If the TLB does not support separate ASIDs, then every time a new table is selected (for instance, with each context switch), the TLB must flushed (or erased) to ensure that the next executing process does not use the wrong translation information

18. Protection
One additional bit is generally attached to each entry in the page table:
a valid-invalid bit.
When this bit is set to "valid," the associated page is in the process's logical address space and is thus a legal (or valid) page.
When the bit is set to" invalid," the page is not in the process's logical address space.
Illegal address references are trapped by use of the valid-invalid bit.
The operating system sets this bit for each page to allow or disallow access to the page.
Together with the validity bit we can create hardware to provide read-only, read-write, or execute-only protection

19. Shared pages
An advantage of paging is the possibility of sharing common code.
One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems)
Similar to multiple threads sharing the same process space
Also useful for interprocess communication if sharing of read-write pages is allowed

20. Paging Tradeoff Paging Advantages:
Easier to allocate the Physical memory from free list of frames.
No External Fragmentation. No Compaction need. The large program different parts could be scattered through many pages.
Easy to "page out" chunks of programs to backing store - All Chunks are the same size (page size) - Easy to provide
Protection
Use valid bit to detect references to "paged-out" pages.
Sharing
Paging Disadvantages:
Can Still have internal fragmentation - process may not use memory in exact multiples of pages
Memory reference overhead - 2 references per address lookup
Paging complex hardware and software implementation.
The Memory required to hold page tables can be large, however it should work very fast.