1. Chapter 7: Main Memory
Rev. by Kyungeun Park, 2017

2. Chapter 7: Memory Management
Background
Swapping
Contiguous Memory Allocation
Paging
Structure of the Page Table
Segmentation
Example: The Intel 32 and 64-bit Architectures
Example: ARM Architecture

3. Objectives
To provide a detailed description of various ways of organizing memory hardware
To discuss various memory-management techniques, including paging and segmentation
To provide a detailed description of the Intel Pentium, which supports both pure segmentation and segmentation with paging

4. Background To keep several processes in memory  Sharing memory !!!
Various ways to manage memory.
Program must be brought (from disk) into memory and placed within a process for it to be run
Main memory and registers are only storage CPU can access directly
Memory unit sees only a stream of memory addresses + read requests, or address + data and write requests.
We are focusing only on sequence of memory addresses already generated by the running program, instead of knowing how they are generated.

5. Background (cont.) Memory management issues: Basic hardware
Binding of symbolic memory addresses to actual physical addresses
Distinction between logical and physical addresses

6. Basic Hardware CPU can directly use main memory and the registers.
Machine instructions refer to memory addresses as arguments, not disk addresses.
Any instructions in execution and any data being used by the instructions:
Must be in direct-access storage devices.
If not, they must be moved into memory.
Register based execution vs. memory-based execution
Memory access takes many cycles of the CPU clock, unlike a register access within one cycle of the CPU clock.
 Processor needs to stall
Remedy:
Add fast memory between the CPU and main memory: Cache
Need Operating System protection from users’ access
User processes also need to be protected from other user processes
 Protection by hardware: base and limit registers

7. Base and Limit Registers
A pair of base (300040) and limit (120900) registers define the logical address space
CPU hardware compares every address generated in user mode with the registers.
Access to operating-system memory or other users’ memory results in a trap to the operating system.
Within each PCB

8. General Hardware Address Protection with Base and Limit Registers

9. Address Binding
Processes (actually programs) on disk, ready to be brought into memory to execute
from the input queue
The first address of the user process need not (cannot) be 0000.
Logical address and physical address mapping
Further, addresses are represented in different ways at different stages of a program’s life
Source code addresses usually symbolic with identifiers (variables or function names)
Compiled code addresses bind to relocatable addresses.
i.e. “14 bytes from beginning of this module”
Linkage editor or loader will bind relocatable addresses to absolute addresses.
i.e
Each binding maps (converts) one address space to another.

10. Multistep Processing of a User Program

11. Binding of Instructions and Data to Memory
Address binding of instructions and data to memory addresses can happen at three different stages
Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes
Load time: Using relocatable code generated at compile time, absolute code can be generated.
Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another
Need hardware support for address mapping (e.g., base and limit registers)

12. Logical vs. Physical Address Space
The concept of a logical address space that is bound to a separate physical address space (central to proper memory management)
Logical address – generated by the CPU; also referred to as virtual address
Physical address – address seen by the memory-management unit
Logical and physical addresses are the same at run time in compile-time and load-time address-binding schemes
Logical (virtual) and physical addresses differ in execution-time address-binding scheme : memory management needed at run time!
Logical address space is the set of all logical addresses generated by a program
Physical address space is the set of all physical addresses corresponding to the logical addresses

13. Memory-Management Unit (MMU)
Hardware device that maps virtual to physical address at run time
Many methods possible, covered in the rest of this chapter
To start, consider simple scheme where the value in the relocation register is added to every address generated by a user process at the time it is sent to memory
Base register now called relocation register
MS-DOS on Intel 80x86 used 4 relocation registers
The user program deals with logical addresses; it never sees the real physical addresses
Execution-time binding occurs when reference is made to location in memory
Logical address bound to physical addresses

14. Dynamic relocation using a relocation register (base register)

15. Dynamic Loading
Dynamic loading: Routine is not loaded until it is called
Better memory-space utilization; unused routine is never loaded.
All routines kept on disk in relocatable load format
Useful when large amounts of code are needed to handle infrequently occurring cases
No special support from the operating system is required  responsibility of the users
OS may help by providing libraries to implement dynamic loading

16. Dynamic Linking
Static linking – system libraries and program code combined by the loader into the binary executable program image
waste of disk space and main memory
Dynamic linking – linking postponed until execution time
Stub, a small piece of code, is included in the image for each library-routine reference
Stub is used to locate the appropriate memory-resident library routine
When the stub is executed, it checks if routine is in processes’ memory address
If not in address space, the program loads the routine into memory address space.
Stub replaces itself with the address of the routine, and executes the routine
Dynamic linking is particularly useful for language libraries  only one copy of the library code
Consider applicability to patching system libraries
Version information is needed
System also known as shared libraries

17. Swapping
A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution
Total physical memory space of processes can exceed physical memory
e.g.) a multiprogramming environment with a RR CPU-scheduling
When a quantum expires, swap starts and CPU-scheduling will be done.
The quantum: large enough to allow reasonable amounts of computing to be done between swaps.
Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images
Roll out, roll in – swapping variant used for priority-based scheduling algorithms;
lower-priority process is swapped out so higher-priority process can be loaded and executed
System maintains a ready queue of ready-to-run processes which have memory images on disk
Does the swapped out process need to swap back into the same physical addresses?
Depends on the address binding schemes :
Assembly or load-time binding : the process cannot be easily moved to a different location.
Execution-time binding : the process can be swapped into a different memory space.
Plus pending I/O to/from process memory space

18. Schematic View of Swapping
Dispatcher checks to see whether the next process in the queue is in memory.
If it is not, and if no free memory region
The dispatcher swaps out a process and swaps in target process.
Then, reloads registers and transfers control to the selected process

19. Context Switch Time including Swapping
Context switch time can then be very high
100MB process swapping to hard disk with transfer rate of 50MB/sec
100 MB/50 MB per second = 2 seconds
Swap out time of 2000 ms (2 seconds)
Plus swap in of same sized process : 2000 ms (2 seconds)
Total context switch swapping component time of 4000 ms (4 seconds)
Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped
Can reduce swap time by swapping out small size of memory  by knowing how much memory really being used
User must keep the system informed of any changes in memory requirements.
A process with dynamic memory requirements need to issue system calls to inform OS of changing memory needs via request_memory() and release_memory().

20. Context Switch Time including Swapping (cont.)
Make sure to swap out an idle process
Plus consider pending I/O
Swap out process P1 and swap in process P2 : I/O operation of process P1 might attempt to use memory now belonging to process P2
 Two main solutions to this problem
1. never swap a process with pending I/O
2. execute I/O operations only into operating-system buffers (kernel space), then transfer between operating-system buffers to process memory then the process is swapped in.
Modified versions of swapping are found on many systems (i.e., UNIX, Linux, and Windows)
Swapping is normally disabled
Swapping will start if more than threshold amount of memory allocated
Swapping is disabled again once memory demand reduced below threshold

21. Swapping on Mobile Systems
Not typically supported
Flash memory based
Small amount of space
Limited number of write cycles
Poor throughput between flash memory and CPU on mobile platform
Instead use other methods to free memory if low
iOS asks apps to voluntarily relinquish allocated memory
Read-only data thrown out and reloaded from flash if needed
Failure to free can result in termination
Android terminates apps if low free memory, but first writes application state to flash for fast restart
Both OSes support paging

22. Contiguous Allocation
Main memory must support both OS and user processes
Limited resource, must allocate efficiently
Main memory usually divided into two partitions:
Resident operating system, usually held in low memory with interrupt vector
User processes then held in high memory
In contiguous memory allocation, each process contained in single contiguous section of memory
Relocation registers with limit register used to protect user processes from each other, and from changing operating-system code and data
Base relocation register contains value of smallest physical address
Limit register contains range of logical addresses – each logical address must be less than the limit register
MMU maps logical address dynamically.
Relocation-register scheme provides an effective way to allow OS’s size to change dynamically  Flexibility
transient operating-system code (uncommon device driver)  removed from memory
Using transient code changes the size of the OS during program execution

23. Hardware Support for Relocation and Limit Registers

24. Contiguous Allocation (Cont.)
Multiple-partition allocation
The simplest method is to divide memory into several fixed-sized partitions
Each partition may contain exactly one process.
Degree of multiprogramming limited by number of partitions
In the variable-partition scheme, a hole – initially, one large block of available memory;
Eventually, a set of holes of various size, scattered throughout memory
When a process arrives, it is allocated memory from a hole large enough to accommodate it
Process exiting frees its partition, adjacent free partitions combined
Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS OS OS OS
process 5
process 5
process 5
process 5
process 9
process 9
process 8
process 10
process 2
process 2
process 2
process 2

25. Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?
First-fit: Allocate the first hole that is big enough
Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size
Produces the smallest leftover hole
Worst-fit: Allocate the largest hole; must also search entire list
Produces the largest leftover hole
According to simulations, first-fit and best-fit are better than worst-fit in terms of speed and storage utilization. First-fit is generally faster.

26. Fragmentation
External Fragmentation – when total memory space exists to satisfy a request, but the available spaces are not contiguous.
Storage is fragmented into a large number of small holes caused by first-fit and best-fit strategies for memory allocation plus variable-partition scheme
Internal Fragmentation – when allocated memory may be slightly larger than requested memory; this size difference is internal to a partition, but not being used
First fit analysis reveals that given N blocks allocated, another 0.5 N blocks are lost to fragmentation
1/3 may be unusable  known as the 50-percent rule

27. Fragmentation (Cont.)
One solution to the external fragmentation : compaction
Shuffle memory contents to place all free memory together in one large block
Move all processes toward one end of memory
All holes move in the other direction with one large hole of available memory produced.
Expensive scheme
Compaction is possible only if:
relocation is dynamic and is done at execution time
Causing I/O problem, solutions are:
Keep jobs in memory while they are involved in I/O
Do I/O only into OS buffers
Another solution to the external-fragmentation problem
permitting the logical address space of the processes to be non-contiguous
Segmentation and paging
Now consider that backing store has the same fragmentation problems as main memory.

28. Segmentation
Segmentation is a memory-management scheme that supports programmer’s view of memory
Segmentation as a hardware supported memory mechanism:
mapping the programmer’s view to the actual physical memory
A program is a collection of segments
A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays

29. Programmer’s View of a Program
Logical address space is a collection of segments.
Each segment has a name and a length.
<segment-number, offset>
While compiling, the compiler automatically constructs segments reflecting the input program.
Since segments vary in length, memory allocation is a dynamic storage-allocation problem.

30. Logical View of Segmentation1 4 2 3 1 2 3 4
user space
physical memory space

31. Segmentation Hardware
Logical address consists of two fields:
<segment-number, offset>
Segment number – an index to the segment table
Offset – be between 0 and the segment limit, if it exceeds the segment limit, trap to OS
Map two-dimensional programmer-defined addresses into one-dimensional physical addresses
Mapping through a segment table – each table entry has:
Segment base – contains the starting physical address where the segments reside in memory
Segment limit – specifies the length of the segment
The segment table is an array of base-limit register pairs.
Segment-table base register (STBR) points to the segment table’s location in memory
Segment-table length register (STLR) indicates number of segments used by a program;
segment number s is legal, if s < STLR

32. Segmentation Hardware (Cont.)
STBR
index
STLR
<segment-number, offset>

33. Example of Segmentation
Separate entry
for each segment

34. Paging
Physical address space of a process is allowed to be noncontiguous; process is allocated physical memory whenever available
Avoids external fragmentation and the need for compaction.
Basic method for implementing paging:
Breaking physical memory into fixed-sized blocks called frames
Dividing logical memory into blocks of same size called pages
When executing a process, its pages are loaded into any available memory frames from their source (a file system or the backing store)
To run a program of size N pages, need to find N free frames and load program
Backing store is divided into fixed-sized blocks that are of the same size as the memory frames
Keep track of all free frames
Still have internal fragmentation

35. Address Translation Scheme
Address generated by CPU is divided into:
Page number (p) – used as an index into a page table which contains base address of each page in physical memory
Page offset (d) – used as a displacement, combined with base address to define the physical memory address that is sent to the memory unit
Page size (frame size) is defined by the hardware.
Size is power of 2, between 512 bytes and 16 Mbytes per page.
For given logical address space 2m and page size 2n
High-order m-n bits of a logical address designates the page number
n low-order bits designate the page offset
Logical address structure:
p is an index into the page table and d is the displacement within the page
page number
page offset p d
m - n n

36. Hardware Support for Paging
Every address generated by the CPU is divided into two parts:
a page number (p) and
a page offset (d)
Page number is used as an index into a page table.
Page table contains the base address of each page (frame) in
physical memory.

37. Paging Model of Logical and Physical Memory

38. logical address = (page no+page offset)
Paging Example
logical address = (page no+page offset)
Ex) 00|00, 00|01, 00|10, 00|11 for
a, b, c, d of page 0
Frame No. 1 2 3 4 5 6 7
Page 0
Frame No.
Page 1
Page 2
Page 3
In the logical address, n=2 (page size) and m=4. (m-n=2 bits for pages)
Using 32-byte (25) physical memory (23=8 pages) of 4-byte(22) sized pages
physical address

39. Page Size Calculating internal fragmentation
Page size = 2,048 bytes (n=11)
Process size = 72,766 bytes
35 pages (71,680 bytes)+ 1,086 bytes
Internal fragmentation of 2, ,086 = 962 bytes
Worst case fragmentation = 1 frame with1 byte
On average fragmentation = 1 / 2 frame size
So small frame sizes desirable. But overhead
Increase in the number of entries in the page table
Each page table entry takes memory to track
Disk I/O burden
As a result, page sizes growing over time
Solaris supports two page sizes – 8 KB and 4 MB

40. Page Table to Physical Memory
page frames
are available.
On a 32-bit CPU,
Each page-table entry is 4 bytes long:
a 32-bit CPU uses 32-bit addresses  a given process space can be 232 bytes (4 GB)
Whereas, system with paging can address 244 bytes (or 16 TB) of physical memory: 4 KB (212) sized page * 232 frames
larger than what can be addressed by the CPU’s logical address: different from the maximum logical size of a process (So, used for additional information)
4 KB (212) page
<Logical address>
page number
page offset
32-bit (4-byte) for page table entry p d
20-bit
12-bit
Page Table
Entries
Frame No.

41. Free Frames – Building Page Table
putting
frame numbers
into its
page table
Before allocation
After allocation

42. Paging Review
Adv.: Clear separation between the programmer’s view of memory and the actual physical memory.
Programmer’s view: as one single space (in fact, scattered)
The mapping is hidden from the programmer and is controlled by the OS.
By implementation, the user process can only access its own memory.
Page table includes only those pages that the process owns.
The OS must be aware of the allocation details of physical memory.
user processes operate in user space
system call (I/O) by a user with an address as a parameter 
the address must be mapped to produce the correct physical address.
OS keeps a copy of the page table for each process like the instruction counter and register contents:
To be used to translate the logical address
To be used by the CPU dispatcher.

43. Implementation of Page Table
Page table for each process is kept in main memory.
PCB contains a pointer to the page table like the other register values, the instruction counter.
Page-table base register (PTBR) points to the page table.
Page-table length register (PTLR) indicates size of the page table.
In this scheme, every data/instruction access requires two memory accesses
One for the page table and one for the data/instruction
The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)
Some TLBs store address-space identifiers (ASIDs) in each TLB entry – uniquely identifies each process to provide address-space protection for that process
Otherwise need to flush at every context switch in order to prevent the next executing process from using the wrong translation information
TLBs typically small (64 to 1,024 entries)
On a TLB miss, value is loaded into the TLB for faster access next time
Replacement policies must be considered
Some entries can not be removed from the TLB (wired down) for permanent fast access
(e.g. TLB entries for kernel code)

44. Associative Memory, TLB
Associative memory – parallel search
Address translation (p, d)
If p is in associative register, get frame # out
Otherwise get frame # from page table in memory
Page #
Frame #

45. Paging Hardware With TLB

46. Effective Access Time
Associative Lookup =  time unit (ignorable time)
Can be < 10% of memory access time
Hit ratio = 
Hit ratio – percentage of times that a page number is found in the TLB
Consider  = 80%,  = 20ns for TLB search, 100ns for memory access
Effective Memory Access Time (EAT)
EAT = 0.80 x x 220 = 140 ns or
EAT = 0.80 x x 200 = 120 ns
Consider slower memory but better hit ratio ->  = 99% for TLB search, 100ns for memory access ( ignored)
EAT = 0.99 x x 200 = 101 ns : only a 1% slowdown in access time

47. Memory Protection
Memory protection implemented by associating protection bit with each frame to indicate if read-only or read-write access is allowed
Can also add more bits to indicate page execute-only, and so on
Valid-invalid bit attached to each entry in the page table:
“valid” indicates that the associated page is in the process’s logical address space, and is thus a legal page
“invalid” indicates that the page is not in the process’s logical address space
Or use PTLR (Page-Table Length Register)
Any violations result in a trap to the kernel

48. Valid (v) or Invalid (i) Bit in a Page Table
Internal
fragmentation
When a program using addresses 0 to 10468:
- Reference to page 6 and 7 is invalid &
- Reference to page 5 is valid upto 12287,
- Reference to [12,888 ~ 16383] is invalid.
- But, causes internal fragmentation of paging
in page 5

49. Shared Pages Advantage of paging is Shared code Private code and data
the possibility of sharing common code
Important in a time-sharing environment
Shared code
One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems)
Reentrant code is non-self-modifying code: it never changes during execution.
two or more processes can execute the same code at the same time.
Similar to multiple threads sharing the same process space
Also useful for interprocess communication if sharing of read-write pages is allowed
Private code and data
Each process keeps a separate copy of the code and data
The pages for the private code and data can appear anywhere in the logical address space

50. Sharing of code in a paging environment
one copy of the editor in physical memory

51. Structure of the Page Table
Memory structures for paging can get huge using straight-forward methods
Consider a 32-bit logical address space as on modern computers
Page size of 4 KB (212)
Page table would have 1 million entries (220 =232 / 212)
If each entry is 4 bytes  4 MB of physical address space / memory for page table
That amount of memory used to cost a lot
Don’t want to allocate page table contiguously in main memory
Solution to this problem is to divide the page table into smaller pieces.
Hierarchical Paging
Hashed Page Tables
Inverted Page Tables

52. Hierarchical Page Tables
Break up the logical address space into multiple page tables
A simple technique is a two-level page table
We then page the page table

53. Two-Level Page-Table Scheme

54. Two-Level Paging Example
A logical address (on 32-bit machine with 1K page size) is divided into:
a page number consisting of 22 bits
a page offset consisting of 10 bits
Since the page table is paged, the page number is further divided into:
a 12-bit page number
a 10-bit page offset
Thus, a logical address is as follows:
where p1 is an index into the outer page table, and p2 is the displacement within the page of the inner page table
Known as forward-mapped page table
page number
page offset p1 p2 d 12 10 10

55. Address-Translation Scheme

56. 64-bit Logical Address Space
Even two-level paging scheme not sufficient
If page size is 4 KB (212)
Then page table has 252 entries
If two level scheme, inner page tables could be 210 entries * 4-byte
Address would look like
Outer page table has 242 entries * 4 bytes per entry = 244 bytes
One solution is to add a 2nd outer page table
But in the following example the 2nd outer page table is still 234 bytes in size
And possibly 4 memory access to get to one physical memory location
outer page
inner page
page offset p1 p2 d 42 10 12

57. Three-level Paging Scheme (64-bit)

58. Hashed Page Tables
Common approach for handling address spaces larger than 32 bits with the hash value being the virtual page number
The virtual page number is hashed into a page table
Each entry in the hash table contains a chain (linked list) of elements hashing to the same location.
Each element contains three fields:
(1) the virtual page number
(2) the value of the mapped page frame
(3) a pointer to the next element in the chain (linked list)
Virtual page numbers are compared in this chain searching for a match
If a match is found, the corresponding physical frame is extracted

59. Hashed Page Table

60. Inverted Page Table
Rather than each process having a page table and keeping track of all possible logical pages, track all physical pages
One entry for each real page (or frame) of memory is added.
Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page
ASID (address-space identifier) in each entry of the inverted page table
Only one page table is in the system.
Simplified version of the inverted page table used in the IBM RT.
Virtual address
<process-id, page-number, offset>
Inverted page-table entry
<process-id, page-number>
where process-id acts like an ASID
If a match is found at entry i  physical address <i, offset> is generated.
If no match is found  an illegal address access

61. Operation of an Inverted Page Table
Entries are sorted according to the physical address;
i is the frame number.
If a match is found at entry i  physical address <i, offset> is generated.

62. Inverted Page Table (cont.)
Decreases memory needed to store each page table with only one table, but increases time needed to search the table when a page reference occurs
Because the inverted page table is sorted by physical address
but lookups occur on virtual addresses
 might need to search the whole table for a match
Use hash table to limit the search to one — or at most a few — page-table entries
TLB (Translation Look-aside Buffers) can accelerate access
But how to implement shared memory?
Shared memory is usually implemented as multiple virtual addresses (one for each process sharing the memory) that are mapped to one physical address.
Because there is only one virtual page entry for every physical page.

63. Oracle SPARC Solaris
Consider modern, 64-bit operating system example with tightly integrated HW
Goals are efficiency, low overhead
Based on hashing, but more complex
Two hash tables
One kernel and one for all user processes
Each maps memory addresses from virtual to physical memory
Each entry represents a contiguous area of mapped virtual memory,
More efficient than having a separate hash-table entry for each page
Each entry has base address and span (indicating the number of pages the entry represents)
TLB holds translation table entries (TTEs) for fast hardware lookups
A cache of TTEs reside in a translation storage buffer (TSB)
Includes an entry per recently accessed page
When virtual address reference occurs, hardware searches the TLB for translation.
If miss, hardware walks through the in-memory TSB, looking for the TTE corresponding to the address (TLB walk)
If match found in the TSB, the CPU copies the TSB entry into the TLB and translation completes
If no match found in the TSB, kernel interrupted to search the hash table
The kernel then creates a TTE from the appropriate hash table and stores it in the TSB, Interrupt handler returns control to the MMU, which completes the address translation.

64. Example: The Intel 32 and 64-bit Architectures
Dominant industry chips
Pentium CPUs are 32-bit and called IA-32 architecture
Current Intel CPUs are 64-bit and called IA-64 architecture
Many variations in the chips, cover the main ideas here

65. Example: The Intel IA-32 Architecture
Supports both segmentation and segmentation with paging
Each segment can be 4GB
Up to 16K segments per process
Divided into two partitions
First partition of up to 8K segments are private to process (kept in local descriptor table LDT)
Second partition of up to 8K segments shared among all processes (kept in global descriptor table GDT)
CPU generates logical addresses: <selector, offset>
Given to segmentation unit which produces a linear address for each logical address
The linear address is given to the paging unit, which generates the physical address in main memory
The segmentation and paging units form the equivalent of the memory-management unit.
Pages sizes can be 4KB or 4MB
<Logical-to-physical address translation in the Pentium>

66. Logical to Physical Address Translation in IA-32
Logical addresses: <selector, offset>
s: segment number
g: GDT/LDT
p: protection 13 1 2
Selector
Linear address (two level paging scheme)

67. Intel IA-32 Segmentation

68. Intel IA-32 Paging Architecture
<Two level paging scheme with p1 and p2 for 4KB page>
<Linear Address>
outer-most
page table
Pages sizes can be 4KB or 4MB.
bypassing the inner page table

69. Intel IA-32 Page Address Extensions
32-bit address limits led Intel to create page address extension (PAE), allowing 32-bit apps access to more than 4GB of memory space
Paging went to a 3-level scheme
Top two bits refer to a page directory pointer table
Page-directory and page-table entries moved to 64-bit in size
Base address of page tables and page frames to extend from 20 to 24 bits
Net effect is increasing address space to 36-bit – 64GB of physical memory

70. Intel x86-64 Current generation Intel x86 architecture
64 bits is ginormous: 264 > 16 exabytes (or 16 quintillion)
In practice only implement 48-bit addressing
Page sizes of 4KB, 2MB, or 1GB
Four levels of paging hierarchy
Can also use PAE, so virtual addresses are 48 bits and 52-bit physical addresses (4096 terabytes)

71. Example: ARM Architecture
Dominant mobile platform chip (Apple iOS and Google Android devices for example)
Apple has licensed the ARM design for its iPhone and iPad mobile devices.
One-level paging for sections, two-level for smaller pages
Modern, energy efficient, 32-bit CPU
4 KB and 16 KB pages: two-level paging
1 MB and 16 MB pages (termed sections): one-level paging
Two levels of TLBs
Outer level has two micro TLBs (one data, one instruction)
Inner is single main TLB
First, address translation at the micro TLB level.
Miss: the main TLB is then checked
Both Miss: normal page table based translation