1. Digital FE-TC4-DC tier for 3D ATLAS pixel at sLHC
March 18th 2010, Marlon Barbero
University of Bonn
Bonn University: D. Arutinov, M. Barbero, T. Hemperek, M. Karagounis, H. Krüger, A. Kruth, N. Wermes.
CPPM Marseille (France): B. Chantepie, J.-C. Clément, R. Fei, D. Fougeron, S. Godiot, P. Pangaud, A. Rozanov.
LBNL Berkeley (USA): J. Fleury, M. Garcia-Sciveres, A. Mekkaoui

2. 3D Front-End for Super-LHC
sLHC tentative layout (>2018): 4 to 5 pixel layers + strip, small radii / large(r) radii (note: Discussion on boundary pixel / short strips, …).
Nigel Hessey
ATLAS present Inner Detector (ID)
tentative ID layout for sLHC?
- All Silicon.
Long Strips/ Short Strips / Pixels.
Pixels:
2 or 3 fixed layers at ‘large’ radii.
2 removable layers at ‘small’ radii.
FE-I4
3D FE

3. FE-TC4
Collaboration Bonn (Germany), CPPM (France), LBNL (USA). MPW organized by FNAL.
Goal: a 50×125 μm2 3D chip, with split analog and digital functionalities.
Technology:
Chartered 130nm (restricted to 5 metals).
Tezzaron 3D.
Analog prototype submitted in 2D Chartered, as technology test bench.
Good performance.

4. FE-I4 architecture & FE-TC4-DC
1st prototype 3D digital based on approx. the same digital organization as ATLAS pixel FE-I4, but with very simplified periphery (smaller too!).
Goal of FE-TC4-DC:
Test 3D for ATLAS with “realistic” architecture.
Straightforward implementation (wrt what we were doing at the time on ATLAS FE).
Test bench for the 4-pixel digital region (one of the main innovation wrt current ATLAS pixel FE, FE-I3).
Test Chartered digital design flow.
Will start by telling more about FE-I4.
Will underline similarities & differences between the 2 FEs.

5. higher hit rate need new FE
Need for a new FE?
Smaller b-layer radius + potential luminosity increase
higher hit rate.
FE-I3 column-drain
architecture saturated.
FE-I4 new digital architecture:
local regional memories,
stop moving hits around (unless RO).
FE-I4 has smaller pixel
(reduced cross-section).
FE-I3FE-I4
100
Inefficiency [%] 80
sLHC
IBL 60 40
FE-I3 at r=3.7 cm!
LHC 20 1 2 3 4 5 6 7 8 9 10
Hit prob. / DC
The “inefficiency wall”

6. FE-I4 4-pixel digital region
4-Pixel Unit
Digital Region
Read & Trigger
Token
disc. top left
disc. top right
hit proc.: TS/sm/big/ToT
5 ToT memory /pixel
disc. bot. left
disc. bot. right
L1T
Read
Neighbor
5 latency counter / region
local storage
low traffic on DC bus
Store hits locally in region until L1T.
Only 0.25% of pixel hits are shipped to EoC  DC bus traffic “low”.
Each pixel is tied to its neighbors -time info- (clustered nature of real hits). Small hits are close to large hits! To record small hits, use position instead of time. Handle on TW.
Consequences:
Spatial association of digital hit to recover lower analog performance.
Lowers digital power consumption (below 10 μW / pixel at IBL occupancy).
Physics simulation  Efficient architecture.

7. pixel array: 336×80 pixels periphery 4-pixel region
DDC & DC
analog 1-pix (FEND)
digital 4-pix (PDR)
pixel array:
336×80 pixels
EODCL
CNFGREG
EOCHL
DACs
DOB
CMD DCD
CREF
periphery
CLKGEN
Power
CalPulse, ADC, TempS, InMUX, EFUSE, AltComp… and more.
Pads
+ Integration & Verification

8. Pixel Region Specs Storage of up to five 4-pixel + neighbor events.
Small / big hit discrimination, 3 programmable modes (of course no discrimination available too). 2 BX association for small hits.
Analog info = 4b ToT.
Neighbor Logic (small hits in adjacent pixels -phi-): 4 bits.
Records up to 16 triggers. Programmable latency up to 255 bunch-crossings.
Stop Mode (record all hits).

9. Digital Region FE-I4 vs Digital FE-TC4: Similarities & Differences
~ “same” 4-Pixel Digital Region:
4b ToT, 5 event storage.
Neighbour.
Small / Big hit discrimination.
up to 16 triggers.
configuration: 4-mask bits (& ANDed region kill).
Added in region: hit memory  alternative double-column level readout shift register (‘à la’ analog tier).
No Hamming coding, no thermal encoder address scheme.
DC token select bit.
Array 14×61 pixels  31 regions (top region has 2 inputs tied low).

10. FE-TC4-DC Periphery Very simplified wrt FE-I4.
3 Shift Registers are multiplexed:
mask SR.
simple readout SR.
configuration (25b): HitDiscr(2), Latency(8), PeriphTokenSel(1), DC Enable(7), DCtokenSel(7).
Main Readout: Trigger-based ToT PISO.
No EOCHL: ‘read’, ‘trigger’, ‘trigger_req’, ‘clock_out’ provided off-FE, ‘token’ signal provided to signify hit.
‘outData’ provides data out, no formatting.
(4b TOT+1b NL)×4 + address (8b) +TriggID (4b) / PDR.
Alternative Readout: Hit info, whole array.
Uses simple readout SR output.

11. Input processing (simple readout)
mask
simple read SR
comparator out
to latency counters & ToT memories:
hit processor
test hit
2x configuration registers: kill & simple read 11 11

12. Hit processing (HC3 mode)- schematic
Receives comparator output
BC resolution
Generates Leading Edge (LE)
Generates Small hit Leading Edge (sLE)
Generates Trailing Edge (TE)
Generates ToT counter reset and enable (rst_cnt, en_cnt) 12 12

13. ToT processing - schematic
Start ToT Counter
Global LE generation (orLE)
Reset memory signal generation (rst_mem)
Memory pointer selection (freeAddr)
Record reset/small in memory
Record neighbor
Record TOT value in memory 13 13

14. Latency Memory/Trigger- schematic
Start/Reset latency counter
Indicate status (full)
Trigger (triggered)
Store/Recognize trigger ID 14 14

15. Periphery Operation Control Read Control Configuration - kill register
- simple read
- global configuration

16. Example readout Pixel Hit Started Latency Counter Trigger
Example of a readout sequence:
Example of a readout sequence:
Example of a readout sequence:
Example of a readout sequence:
Example readout 1 2 3 4 5
Pixel Hit
Started Latency Counter
Trigger
Read Data From Region/Pixel
Shift Data Out

17. Chip Layout Power consumption ~5.5mW (~7μW/pixel).
pad 95
pad 7
pad 20
pad 95
Power consumption ~5.5mW (~7μW/pixel).
1.2V,25C, TT, 40MHz, 4hit/BC/chip.

18. Conclusion
A 3D prototype was designed and submitted, as a test bench for this technology, in framework of ATLAS pixel upgrade for higher luminosities.
Submitted Digital ‘DC’ Tier: Based on FE-I4 architecture.
Plans:
Prototyping blocks in 2D Chartered in Summer (e.g. FEND, CREF, CLKGEN, new LVDS…).
Design a 3D equivalent to FE-I4.
Start studying constraints & specs for sLHC innermost layer digital architecture: Inefficiencies, Bandwidth, …
New clustering algo? New region structure? New digital organization? (new analog? need for ToT?)

19. Schedule Goal: Full size FE-TC4-A Dec. 2010. Constraints:
Learn from FE-TC (1st MPW)  Studied early summer.
Learn from FE-I4 (Subm. March/April)  Studied summer.
Learn from 2D Chartered run (Subm. June)  Back September.
Irradiation.
Design a complex 3D 20 mm by 19 mm IC.
Next meeting 3D consortium:
(TWEPP Sept. Aachen)
Why not Bonn? Th./Fr. week before or Mo./Tu. week after. (I will start checking feasibility)
…3D!?
Ludwig van Beethoven

20. BACKUP
BACKUP

21. FE-I4 Digital DC / Data transfer
Made of pixel digital region.
In DC, Token based readout (dual token scheme DC / EoC with triple redundancy + majority voting).
21 4-pixel digital region the base structure for clock / buffering:
Skew-compensated clock routing  ~0.8ns skew for all pixels of array?
Buffering of read / L1T.
Data transferred to FIFO asap. All controlled by EOCHL.
Address transfer with minimal number of gates for yield enhancement (thermal encoder scheme). Data + Address is hamming coded, decoded and corrected before data compression block.

22. Performance / Efficiency
IBL: charge sharing in Z comparable to phi
Regional Buffer Overflow
Memories
Simulation
Analytical
IBL
10xLHC 5
0.047%
2.19%
0.029%
2.25% 6
0.011%
0.65%
0.003%
0.57% 7
<0.01%
0.16%
0.13%
η=0
@ IBL rate, pile-up inefficiency is the dominant source of inefficiency
Inefficiency:
Pile-up inefficiency (related to pixel x-section and return to baseline behavior of analog pixel)  ~ 0.5%.
Regional buffer overflow  ~0.05%.
Inefficiency under control for IBL occupancy.
Mean ToT = 4
0.6%

23. FE-I4 / FE-I3
FE-I3 18
160
FE-I4

24. FE-I4 for IBL & sLHC
ATLAS Pixel Detector
3 barrel layers / 3 end-caps
end-cap: z± 49.5 / 58 / 65 cm
barrel: r~ 5.0 / 8.8 / 12.2 cm
Present beam pipe & B-Layer
IBL (~2014): inserted layer in current pixel detector.
- All Silicon.
Long Strips/ Short Strips / Pixels.
Pixels:
2 or 3 fixed layers at ‘large’ radii (large area at 16 / 20 / 25 cms?)
2 removable layers at ‘small’ radii
sLHC tentative layout (>2017): 4-5 pixel layers, small radii / large(r) radii (note: Discussion on boundary pixel / short strips, …).
FE-I4
Existing B-layer
r~37 mm
New beam pipe
IBL mounted on beam pipe

25. Pixel Layout
250 mm
TDAC
Amp2
synthezised digital region (1/4th )
50 mm
discri
Preamp
FDAC
Config Logic
Note: Digital ground tied to substrate, mixed signal environment BUT digital region placed in “T3” deep n-well.

26. Future FE-I4-Based Module (& Consequences for FE-I4)
Flex 4
Sensor 4 1 3
FE-Chip 2 1 3 2 5
1) Big chip (periphery on one side of module).
2) Reduce size of periphery (2.8 mm2 mm).
3) Thin down FE chips (190 μm90 μm).
4) Thin down the sensor (250 μm 200 μm)?
5) Less cables (powering scheme)?
Increased active area: from less than 75 % to ~90 %:
 Reduced periphery; bigger IC; cost down for sLHC (main driver is flip-chip costs per chip).
No MCC:
 More digital functionality in the IC.
Power:
 Analog design for reduced currents; decrease of digital activity (digital logic sharing for neighbor pixels); new powering concepts. 8 metal layers [2 thick Alu.]  power routing.
challenging: power (routing, start-up), clk. distrib., simulation / management, yield

27. Memory Management - schematic
Selects free memory
Token management
Selects triggered memory during read
Enables outputs
Design: x5 latency cell 27 27