1. Integrated Shunt-LDO Regulator for FE-I4
Michael Karagounis, David Arutinov Universität Bonn
Power Distribution Working Group Meeting Feb. 24th 2009

2. Serial Powering Topology
modules are powered in series by a constant current source
parallel placed FE-I4 chips at module level
integrated regulation circuitry in every FE-I4 chip  avoid additional components on the module  redundancy
two different supply voltages per FE-I4 chip needed (1.5V & 1.2V)
Regulators should be able:
to operate in parallel
generate different output voltages

3. LDO Regulator with Shunt Transistor (ShuLDO)
Simplified Schematic
Combination of LDO and shunt transistor
M4 shunts the current not drawn by the load
Fraction of M1 current is mirrored & drained into M5
Amplifier A2 & M3 improve mirroring accuracy
Ref. current defined by resistor R3 & drained into M6
Comparison of M5 and ref. current leads to constant current flow in M1
Ref. current depends on voltage drop VIin which again depends on supply current Iin
„Shunt-LDO“ regulators having completely different output voltages can be placed in parallel without any problem regarding mismatch & shunt current distribution
Resistor R3 mismatch will lead to some variation of shunt current (10-20%)
„Shunt-LDO“ can cope with an increased supply current if one FE-I4 does not contribute to shunt current e.g. disconnected wirebond  ref current goes up
Can be used as an ordinary LDO when shunt is disabled
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4. Shunt - LDO Voltage Current Characteristic
Simulation
Current flowing through the regulator (Power PMOS transistor M1)
Vout Regulator output voltage (green)
Vin potential between Iin & Iout (blue)
linear voltage to current characteristic
slope is defined by reference resistor R3 divided by the current mirror aspect ratio 2kOhm/1000=2Ohm
Output voltage stays stable as soon the amplifiers are saturated and the final value is reached.

5. Parallel Regulator Operation
Simulation
Vout=1.5
Vout=1.2
2 regulators placed in parallel with Vout1=1.2 and Vout2=1.5
Output voltages settle at different potentials
Current flowing through the regulator stays the same

6. Setup for Test Measurements
Two Shunt – LDO regulators are connected in parallel on-chip  avoid influence of PCB parasitics
biasing & reference voltage is provided externally
input & load current is provided by programmable Keithley sourcemeter
input & output voltages are measured automatically using a Labview based system
developed by D. Arutinov

7. Two Shunt-LDO parallel connected on-chip
Measurement
Simulation
Saturation point is reached for smaller input currents and is more abrupt than in simulation
Non constant slope of Vin
Vout1 and Vout2 slightly decrease with rising input current  IR drop on ground rail leads to smaller effective reference voltage
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8. Load Regulation Measurement
Iin = 800mA
1.5V output voltage sees a fix load I=400mA 1.2V output has variable load Iload
1.2V output voltage sees a fix Iload=400mA 1.5V output has variable Iload
Input & output voltages collapse when the overall load current reach the input current value
Effective output impedance of R = mOhm (incl. wire bonds & PCB traces)

9. Setup for Measurement of Shunt Currents
direct measurement of shunt current distribution is not possible  regulators are connected in parallel on-chip
shunt capability can be switched-off by defining zero reference current  use of special dedicated bond pads
two SHULDO test chips connected in parallel on PCB level  each test chips has one operational regulator and one regulator switched-off
shunt current is measured by 10 mOhm series resistors & instrumentation opamp
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10. Single Shunt Operation
Measurement
Simulation
Input voltage potential level around ~1.9 is reached with half of the current (500mA) with respect to parallel operation of two regulators
 Shunt capability of 2nd regulator is switched-off
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11. Current Distribution Measurement
preliminary
Unbalanced shunt current distribution unless both regulators are saturated
More shunt current is flowing through the regulator which saturates first
Non-constant slope of input Voltage closely related to shunt current distribution
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12. Reason for Unbalanced Shunt Current Distribution
Bad mirror accuracy for non saturated transistors
Current drained by non-saturated MOS transistors depends on Vds
Offset of diff. amplifier A2 leads to different Vds voltages across M1 & M2  wrong current is compared to the reference
Because of high current mirror aspect ratio (1000) even a small Vds mismatch leads to a big shunt current mismatch
Current drained by saturated transistor is less dependent on Vds  improvement of shunt distribution as soon both transistors are saturated
detailed Monte-Carlo study needed to reduce offset
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13. Shunt Current Simulation with Offset Voltage
Offset voltage of 20 mV leads to simulation result similar to measurement results
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14. Conclusion & Plans
Shunt-LDO working principle demonstrated by prototype
 Parallel connected regulators generate different output voltages out of a single current supply
Stable operation of Shunt – LDO regulator observed (no oscillations)
Prototype study revealed circuit part which is crucial for balanced shunt current distribution
More regulator characteristics to be studied by measurements
 Real serial powered system to be developed
 Test of pure LDO regulator operation with shunt capability switched-off
Detailed Monte-Carlo study for reduction of voltage offset in current mirror amplifier
Integration of biasing and reference voltage circuits Next Submission: March, 16th
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15. Spare Slides: Shunt Current Distribution
Two parallel connected Shunt-LDO regulators with same output voltage shunt the same current during power up
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16. Spare Slides: Shunt Current Distribution
output voltage is changed with both regulators beeing saturated
Vout1 fixed at 1.2V
Vout2 varies ( 1.2V – 1.5V )
shunt current changes about 8 mA  1.4 %

17. Spare Slides: Load Transient Behaviour
load current pulse of 150mA 15mV measured across 100mOhm
10mV output voltage change
measured output impedance Rout=66mOhm including wire bonds & PCB traces
Slide 17