1. SLAC I&C Division / EE Department
2012 EPICS Timing Workshop
The Accelerator Timing System at SLAC: Experiences, Ideas & Future Plans
John Dusatko
SLAC I&C Division / EE Department

2. Introduction
This talk will focus on the SLAC Timing System giving a bit of history up to the development of the LCLS-I timing system and relate some of our experiences from that.
This is followed by a description of our plans for LCLS-II and other systems
Finally, I’ll present some ideas/wishlist for new features

3. Background / History
Legacy Timing System: Developed in the 1980s for the SLC:
CAMAC-based, generates triggers based on six AC mains-derived “Timeslot” signals
Whole system triggered off of 360Hz “Fiducial” (Generated from the three AC mains phases)
Uses obsolete components
*Still* in use (ran part of LCLS-I before upgrade and still running FACET)
LCLS-I:
Gave us the chance to develop a new timing system:
Decision to use MRF Event System
Had to co-exist with original SLC timing and was initially slaved to it (no longer following upgrade)  This requirement affected some of our design decisions

4. LCLS-I Timing/Event System Architecture~
Linac main drive line
Low Level RF
Fiber Cable
TRD Rx
FIDO
PDU
Linac Master Osc
Raw 360 Hz
LCLS Timeslot Trigger
LCLS Master
Oscillator
476
MHz
TRD Tx
Sync/Div
119Mhz + FID
TO:
- Cav BPM
- MPS BLM
- MPS PIC
- BCS
Sq Wave on Coax
119Mhz + FID
Sq Wave on Coax
360 Hz
119 MHz
TRD Rx
fiber
distribution
SLC
MPG P N E T I O C E V G F A N
SLC
events
LCLS
events
LCLS-I Timing as originally implemented / Slaved to SLC Timing: formed event codes from SLC Timing Pattern (PNET)
Master Pattern Generator
EPICS Network
Digitizer
LLRF
BPMs
Toroids
Cameras
Wire Scanner
SLC klystrons I O C E V R D E V
LCLS Timing System components are in RED
TTL m P P N E T P D U
TTL-NIM
convert.
SLC Trigs

5. LCLS-I Timing/Event System Architecture
Linac main drive line ~
Fiber Cable
FIDO
PDU
TRD Rx
Linac Master Osc
Raw 360 Hz
LCLS Timeslot Trigger
LCLS Master
Oscillator
476
MHz
Sync/Div
119Mhz + FID
TRD Tx
TO:
- Cav BPM
- MPS BLM
- MPS PIC
- BCS
Sq Wave on Coax
119Mhz + FID
Sq Wave on Coax
360 Hz
119 MHz
TRD Rx V M T G C P U E V G F A N
60Hz
Timeslot 1
LCLS
events
Fiber
distribution
IRQ &
Timeslot
From
MPS
(Enet)
Digitizer
LLRF
BPMs
Toroids
Cameras
Wire Scanner
SLC klystrons
EPICS Network C P U E V R D E V
TTL
LCLS-I Timing De-Coupled from the SLC System. VMTG module provides Timeslot info and CPU forms event codes directly. The LCLS-II Timing System will look very similar to this
TTL-NIM
convert.

6. LCLS-I Timing System Features & Comments:
Has ~122 EVRs across 1.5KM of machine (not counting dev units)
85 PMC EVRs
37 VME EVRs (LLRF & BPM Subsystems)
Due to distances, we had to use Single-Mode Fiber (replaced Multi-Mode SPFs with SM)
Developed Separate TRD (Timing Reference Distribution) subsystem to provide 119MHZ w/360Hz phase-modulated fiducial to systems that didn’t need overhead of an EVR
Developed Custom HW (Sync/Div, TRD, VMTG) in addition to MRF Event HW
Extensive SW development effort (more so than the HW dev)
Made some changes to MRF HW

7. LCLS-II will timing will be very similar to LCLS-I
LCLS-II Timing System
LCLS-II will timing will be very similar to LCLS-I
Have its own EVG
LCLS-II will run on different timeslots than LCLS-I
Both LCLS-I & -II timing systems will “know” about each other (via a synchronizing signal)
Using uTCA platform as well as VME

8. LCLS-II Timing System Micro TCA
Will be used in at least the BPM subsystem, possibly LLRF as well
Development effort underway
Interim timing solution: PMC-EVR-200 on uTCA adapter
Planning on using/adapting Stockholm University uTCA Timing Module (dev’d for XFEL) as final solution
Developed for XFEL
Distributes triggers & clock on uTCA backplane
Double-wide (with RTM I/O) in development
Contains fiber phase stabilization mechanism

9. Other SLAC Machines & Future Plans
FACET: (1st 2/3rd of Linac)
Uses SLC timing for all Legacy Systems
Uses Event System for all new subsystems (accelerator controls as well as experiments)
XTA: X-Band Test Accelerator (stand-alone machine)
Uses Event System for timing / coupled to SLC timing
SPEAR-III:
Considering Event System for booster upgrade
PEP-X:
Could/Would use Event System in some form
Grand SLAC Timing System:
Would tie together all related systems (don’t know what this would look like yet…)

10. Timing Features Wishlist
Desired Features:
EVR Standby trigger capability
FPGA Gateware mod to EVR to support stby triggers (completed on VME-EVR)
Greater than 256 event codes
Experiment support keeps asking for more ECs!
Fanout Module Upgrade
Added diagnostics for SFP status readout & single-level fanout ports
Fiber Phase Stabilization
SU uTCA module has this feature
Additional Diagnostics on EVG side
Readout of parameters (RF power, phase, fiducial rate, etc.) from Sync/Div chassis
EVR SFP (optical xcvr) Diagnostics
Readout for maintenance