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Chapter 6
High-Speed CMOS Logic Design
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.

2. 6.1 Introduction

3. 6.1 Introduction

4. 5.6.1 Basic Bistable Circuit

5. 6.1 Introduction

6. 6.2 Switching Time analysis

7. 6.2 Switching Time Analysis

8. (6.1) (6.2) (6.3) 6.2 Switching Time Analysis Propagation delay time
for Low-to-High case :
for High-to-Low case :
average propagation delay time :
(6.1)
(6.2)
(6.3)

9. (6.4a) (6.4b) 6.2 Switching Time Analysis NMOS device (pull-down)
(n-channel device saturation current : )
propagation delay time :
& (Chapter 5)
therefore
(6.4a)
(6.4b)

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11. (2.25) 2.5.2 Current Equations for Velocity-Saturated Devices
Linear region operation
(2.25)

12. 2.5.2 Current Equations for Velocity-Saturated Devices
Saturation region operation
Limiting cases :
( )
( )
(2.26)
(2.27)
(2.28)
(2.29)

13. (6.5a) (6.5b) 6.2 Switching Time Analysis PMOS device (pull-down)
(p-channel device saturation current : )
propagation delay time :
therefore
(6.5a)
(6.5b)

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15. (6.6) 6.2 Switching Time Analysis refer to the example 6.1 (p.254)
equvalent resistance for SPICE simulation
sheet resistance :
total resistance
(6.6)

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17. 6.2.1 Gate Sizing Revisited-Velocity Saturation Effects

18. 5.2.3 Voltage Transfer Characteristics (VTC) of CMOS Gates

19. 6.2.1 Gate Sizing Revisited-Velocity Saturation Effects

20. 6.2.1 Gate Sizing Revisited-Velocity Saturation Effects

21. 6.3 Detailed load capacitance calculation

22. 6.3 Detailed Load Capacitance Calculation
(6.7)

23. 6.3.1 Fanout Gate Capacitance

24. 2.8 Capacitances of the MOS Transistor

25. 2.8.1 Thin-Oxide Capacitance

26. (2.34) 2.8.1 Thin-Oxide Capacitance
Total capacitance of the thin-oxide :
Trends :
i) technology, oxide thickness
ii) process, with
iii) process, with tox=22 ang.
(2.34)

31. (6.8) (6.9) 6.3.1 Fanout Gate Capacitance Total fanout capacitance :
Total input capacitance
for technology
therefore, redefine
(6.8)
(6.9)

32. 6.3.1 Fanout Gate Capacitance
For an inverter
total fanout capacitance :
For NANDs, NORs, or other complex gates

33. 6.3.2 Self-Capacitance Calculation

34. 6.3.2 Self-Capacitance Calculation

35. (6.10) 6.3.2 Self-Capacitance Calculation
Total self-capacitance of the inverter
Effective capacitance per width
(6.10)

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41. 6.3.2 Self-Capacitance Calculation

42. (6.11) 6.3.2 Self-Capacitance Calculation
Self-capacitance at the ouput node
(6.11)

43. 6.3.2 Self-Capacitance Calculation

44. 6.3.3 Wire Capacitance
Wire capacitance
(6.12)

45. 6.7 Summary
Propagation delay :
Driving resistance :
Load capacitance :
Input capacitance :
Self-capacitance :
Wire capacitance :
Total delay :

46. 6.4 Improving Delay calculation with input slope

47. 6.4 Improving Delay Calculation with Input Slope
(6.13)

48. 6.4 Improving Delay Calculation with Input Slope

49. 6.4 Improving Delay Calculation with Input Slope

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54. (6.14) 6.4 Improving Delay Calculation with Input Slope
Total delay for ramp input
(according to the example above)
therefore
(6.14)

55. 6.4 Improving Delay Calculation with Input Slope
(6.15)

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58. 6.7 Summary
Propagation delay :
Driving resistance :
Load capacitance :
Input capacitance :
Self-capacitance :
Wire capacitance :
Total delay :

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64. 6.5 Gate Sizing for optimal path delay

65. 6.5.1 Optimal Delay Problem

66. 6.5.1 Optimal Delay Problem

67. 6.5.1 Optimal Delay Problem

68. 6.5.2 Inverter Chain Delay Optimization – FO4 Delay
Input capacitance of gate
effective output resistance
therefore, time constant
(6.16)
(6.17)
(6.18)

69. 6.5.2 Inverter Chain Delay Optimization – FO4 Delay

70. (6.19) (6.20) 6.5.2 Inverter Chain Delay Optimization – FO4 Delay
Delay time
ratio of self-capacitance to input capacitance
(6.19)
(6.20)

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72. 6.5.2 Inverter Chain Delay Optimization – FO4 Delay

73. 6.5.2 Inverter Chain Delay Optimization – FO4 Delay
Total delay time
delay term depend upon the size of inverter j

74. 6.5.2 Inverter Chain Delay Optimization – FO4 Delay

75. 6.5.2 Inverter Chain Delay Optimization – FO4 Delay
Using Figure 6.22
Delay time
(using )
gate :
total : ,
(6.21)
(6.22)
(6.23)

76. 6.5.2 Inverter Chain Delay Optimization – FO4 Delay

77. 6.5.2 Inverter Chain Delay Optimization – FO4 Delay

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80. 6.5.3 Optimizing Paths with NANDs and NORs

81. (6.24) 6.5.3 Optimizing Paths with NANDs and NORs Total delay
for NAND chain
for NOR chain
Intrinsic time constants
for NAND
for NOR
(6.24)

82. 6.5.3 Optimizing Paths with NANDs and NORs

83. (6.25) 6.5.3 Optimizing Paths with NANDs and NORs Total delay
Delay through stages j and j+1
(6.25)

84. (6.25) 6.5.3 Optimizing Paths with NANDs and NORs
Delay through stages j+1 and j+2
(6.25)

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87. 6.6 Optimizing paths with logical effort

88. (6.25) 6.6.1 Derivation of Logical Effort Total delay Delay equation
; fanout
; parastic term
(6.25)

89. 6.6.1 Derivation of Logical Effort

90. 6.6.1 Derivation of Logical Effort

91. 6.6.1 Derivation of Logical Effort
Parameters - LE values

92. 6.6.1 Derivation of Logical Effort
Parameters - LE values
(using capacitance ratios)
(using equvalent resistances)

93. 6.6.1 Derivation of Logical Effort

94. 6.6.1 Derivation of Logical Effort
Paramters - P values
for NAND
for NOR

95. 6.6.1 Derivation of Logical Effort

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98. 6.6.2 Understanding Logical Effort

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105. 6.6.3 Branching Effort and Sideloads

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110. 6.7 summary

111. 6.7 Summary
Propagation delay :
Driving resistance :
Load capacitance :
Input capacitance :
Self-capacitance :
Wire capacitance :
Total delay :

112. 6.7 Summary
Inverter delay equation :
where ,
Intrinsic time constants

113. 6.7 Summary
Normalized delay equation :
where
LE(Logical Effort) for inverter, NAND2, and NOR2
Path effort

114. 6.7 Summary
Optimal stage effort :
Gate sizing based on optimal stage effort
Normalized delay :