1. Yu Li State Key Laboratory of Particle Detection and Electronics
Readout electronics for a boron-coated multi-wire proportional chamber neutron detector
Yu Li
State Key Laboratory of Particle Detection and Electronics
Good afternoon /morning, ladies and gentleman. My name is yuli, I am a doctor in the State Key Laboratory of Particle Detection and Electronics.
The title of my report is Readout electronics for a boron-coated multi-wire proportional chamber neutron detector. Then I will detail introduce my work.

2. Introduction Design Summary
Frist, introduced the structure of boron-coated MWPC detector.
We know neutron is an ideal probe for studying dynamical properties and the structure of matter.Traditionally, most of the neutron scattering spectrometers adopt (helium 3)3He gas neutron detector. However, in recent years, the shortage of 3He gas brings challenge for the usage of this kind of detector in new applications. In order to solve this problem, we find 10B (boron 10) can absorb neutrons and the reaction process is introduced here. And the reaction products are easy to measure.
So the Institute of High Energy Physics(IHEP) design a two dimensional boron-coated MWPC detector. The structure of the detector is shown on the left. In the detector, the incident window is covered by boron converter, and the secondary particles enter the electric field and cause avalanche near the anode wire. Induced current is extracted from the readout electrode for further processing. And the picture of detector is shown on the right.
The parameters of this detector is described here, the effective area is about 20 centimeter multiply 20 centimeter. The distance from incident window to cathode plane is 8 millimeter and from anode plan to cathode plane is 3 millimeter; The distance between anode wire is 2mm, the diameter of anode wire is 25μm(micrometer)； The distance between cathode wire spacing is 1mm, the diameter of cathode is 50μm.

3. Introduction Challenge : shortage of 3He gas
A two dimensional boron-coated MWPC detector is designed here
We know neutron is an ideal probe for studying dynamical properties and the structure of matter.Traditionally, most of the neutron scattering spectrometers adopt (helium 3)3He gas neutron detector. However, in recent years, the shortage of 3He gas brings challenge for the usage of this kind of detector in new applications. In order to solve this problem, we find 10B (boron 10) can absorb neutrons and the reaction process is introduced here. And the reaction products are easy to measure.
So the Institute of High Energy Physics(IHEP) design a two dimensional boron-coated MWPC detector. The structure of the detector is shown on the left. In the detector, the incident window is covered by boron converter, and the secondary particles enter the electric field and cause avalanche near the anode wire. Induced current is extracted from the readout electrode for further processing. And the picture of detector is shown on the right.
The parameters of this detector is described here, the effective area is about 20 centimeter multiply 20 centimeter. The distance from incident window to cathode plane is 8 millimeter and from anode plan to cathode plane is 3 millimeter; The distance between anode wire is 2mm, the diameter of anode wire is 25μm(micrometer)； The distance between cathode wire spacing is 1mm, the diameter of cathode is 50μm.

4. Introduction Design Summary
Frist, introduced the structure of boron-coated MWPC detector.
We know neutron is an ideal probe for studying dynamical properties and the structure of matter.Traditionally, most of the neutron scattering spectrometers adopt (helium 3)3He gas neutron detector. However, in recent years, the shortage of 3He gas brings challenge for the usage of this kind of detector in new applications. In order to solve this problem, we find 10B (boron 10) can absorb neutrons and the reaction process is introduced here. And the reaction products are easy to measure.
So the Institute of High Energy Physics(IHEP) design a two dimensional boron-coated MWPC detector. The structure of the detector is shown on the left. In the detector, the incident window is covered by boron converter, and the secondary particles enter the electric field and cause avalanche near the anode wire. Induced current is extracted from the readout electrode for further processing. And the picture of detector is shown on the right.
The parameters of this detector is described here, the effective area is about 20 centimeter multiply 20 centimeter. The distance from incident window to cathode plane is 8 millimeter and from anode plan to cathode plane is 3 millimeter; The distance between anode wire is 2mm, the diameter of anode wire is 25μm(micrometer)； The distance between cathode wire spacing is 1mm, the diameter of cathode is 50μm.

5. System architecture of the readout electronics
MWPC detector combined with delay line module
Low noise amplifier
lead edge timing
Based on FPGA carry4 resource
based on SoC FPGA technology
In order to measure the neutron hit position of MWPC detector that we mention above. There are three methods for selection. But considering the position accuracy, the cost and complexity of readout electronics, we choose the delay line readout method. The theory of delay line method is described here : In the readout electronics, by recording the time difference between the two pulses from two ends of the delay line module, because this time interval conveys information about the neutron impact position, the hit position can be reconstructed.
So we design the readout electronics system like the figure shows, first part is detector and delay line module, second part is the front-end electronics board, it can realize low noise amplifier and using the method of lead edge timing. So the output signal of delay line module are conditioned with differential Low Voltage Differential Signal (LVDS) by FEE module. The leading edge of LVDS indicates the timing information. This timing signal is sent to TDC for time information measurement. For the purpose of precision, simplicity and flexibility., TDC is implemented in FPGA. The time data are transmitted to computer over gigabit Ethernet implemented with SoC FPGA technique.
Delay line readout method

6. Analysis of delay line module(1)
is timing jitter;
is the slope of the signal;
is the noise which is introduced by the termination resistance
Fig.1 Relationship between signal timing jitter and noise
Because of and eq.(1), we can get the
expression (2)
(2)
From figure 1, we know the relationship between noise, timing jitter and the slope of the signal, so an expression (1) can be get. And the noise is introduced by the termination resistance .
Based on the formula (1), a further consideration about timing jitter and total propagation time can be put forward. In order to achieve good positioning resolution, (deta t Divide T ) must be as little as enough. And based on detaV equal to detaI multiply Rz and expression(1), we can get expression (2).
From the expression (2), two conclusions can be obtained, the first is 念PPT。
Conclusion :
The bigger the value of Rz, the better the position resolution；
The bigger the value of , the better the position resolution.

7. Analysis of delay line module(2)
Fig.2 Structure of readout wire induced charge distribution
Fig.3 Equivalent model of delay line module
Because of the design of delay module is suitable or not can finally decide position resolution, a detail analysis of delay line module will introduce here.
The signal readout module can be modelled as Fig.1. The readout wires are connected to one tap of the delay line chain in groups of four.
In many references, the induced current pulses on readout wires near the point can be expressed as (1). where D is the spacing between anode and cathode plane, S is the cathode wire spacing, i is the cathode wire number where avalanche occurs and k is the wire number.
Next, introduce the equivalent module of delay line. Because of the value of parasitic resistance is small enough to be ignored, the whole delay line chain module can be modelled as multi low-pass LC filter, which is shown in Fig. 2.
Within the bandwidth considered, the impedance of inductance is much smaller than that of capacitance, So the approximate transfer function of delay line can be denoted as (2). where L is the value of inductance, C is the value of capacitance, RZ is termination matching resistance, δ is delay time of each delay tap, n is the number of taps to pass through.
Calculating the convolution of the inducted current pulse (1) with the transfer function (2) will yield the output signal ik_out. With the change of cathode wire number k, the output signal ik_out of any cathode wire can be get. So the total output current can be accumulated by the output signal ik_out.
Then the total output current of delay line module can be expressed as eq. (3) and eq. (4). The total number of cathode wire is 200 and cathode wires are connect to one delay line tap in group of four (shown in Fig. 1), u(t) is the step function, Ileft is the total output current from the left side of the delay line chain, while Iright is the right side one.
(3)
(4)
L is the value of inductance;
C is the value of capacitance;
RZ is termination matching resistance;
δ is delay time of each delay tap;
n is the number of taps to pass through.
D is the spacing between anode and cathode plane;
S is the cathode wire spacing;
i is the cathode wire number where avalanche occurs; k is the wire number.

8. Analysis of delay line module(3)
(1)
(5)
Calculating the convolution of the inducted current pulse (3) with the transfer function (4) will yield the output signal ik_out, Ileft and Iright can be expressed as eq. (6) and eq. (7).
(6)
Calculating the convolution of the inducted current pulse (1) with the transfer function (2) will yield the output signal ik_out. With the change of cathode wire number k, the output signal ik_out of any cathode wire can be get. So the total output current can be accumulated by the output signal ik_out.
Then the total output current of delay line module can be expressed as eq. (3) and eq. (4). The total number of cathode wire is 200 and cathode wires are connect to one delay line tap in group of four (shown in Fig. 1), u(t) is the step function, Ileft is the total output current from the left side of the delay line chain, while Iright is the right side one.
u(t) is the step function;
Ileft is the total output current from the left side of the delay line chain, while Iright is the right side one.
(7)

9. Analysis of delay line module(4)
The bigger the value of , the better the position resolution.
Taking into account of , where I is express in (6):
After the front analysis, the conclusion about how to design delay line module is pu forward: first is the bigger the value of Rz, the better the position resolution；second is the bigger the value of 公式 , the better the position resolution.(read ppt).
Now taking into account of 公式 , where I is express in (3) which is mentioned above. So we can get the value of 公式 with different parameters of delay line module for different area of MWPC detector， which is shown in figure 4.
念绿框中的内容From fig.4, when the area of MWPC is 20cm*20cm, the number of delay line taps is 50, from the left figure, =5ns will make maximum, however, when the area of MWPC is 40cm*40cm, the number of delay line taps is 50, from the left figure, =2ns will make maximum.
Fig.4 The value of with different parameters of delay line module for different area of MWPC detector
From fig.4, appropriate value of δ for different area of the detector can get better position resolution

10. Structure of the FEE module
As shown in Fig.4, Fast current amplifier with two-stage structure is used to achieve advantages of high gain, high bandwidth and low noise.
Fig.4 Diagram of cathode preamplifier board
Fig. 5 shows the diagram of cathode preamplifier board. In order to achieve high gain, high bandwidth and low noise, CPB adopts two stages of amplifier, the first stage use
a trans-impedance amplifier and the second one use a current feedback amplifier as. Between the two stages, there is a RC circuit coupling to eliminate the influence of voltage drift. At last, amplified signal is fed into a discrimination and signaled out with LVDS level for the purpose of transmitting to backend time digitizing.
For the purpose of evaluating the performance of the front-end electronics, we make some tests in the laboratory, the results are shown in figure 5, the linear range of cathode preamplifier board is about 0 μA-33 μA; the bandwidth of it is about 19.2MHz, and the Output noise of it is about 5.3mV.
Fig. 5. Test results of the cathode preamplifier board: (a) Input-Output curve. (b) Amplitude-Frequency curve. (c) Output noise with suspended input.
The performance of cathode preamplifier board: (a) the linear range is 0 μA-33 μA;
(b) bandwidth is 19.2MHz; (c) Output noise is about 5.3mV.

11. Structure of time digitizing module
Fig.4 The architecture of the time digitizing module and picture of it
Fig.5 Schematic diagram of TDC
Figure. 4 shows the structure of TDC, One TDC module can receives 4 channels anode signal and 16 channels cathode signal from four layers of boron-coated MWPC detectors.
And TDC module use coarse and fine time measurement method, Coarse time measurement utilizes a normal binary counter to achieve coarse time, which is a multiple of the clock period. The fine time is measured by interpolation method which is less than one clock period. Fine time measurement utilizes dedicated carry chain resources in the FPGA to construct a delay chain for time interpolation.
To evaluate the time measurement resolution of TDC module. Do some lab tests, the result is show in the figure, Time measurement resolution is better than 35 ps (RMS）
Timing digitizing module use coarse and fine time measurement method and implemented in Xilinx FPGA.
The time measuremenresolution of TDC is better than 35ps(RMS).

12. Experiment and verification
Fig.6 The linear curve of the number of delay tap and time different of delay line module with 5ns tap value
Fig.7 The resolution of time difference with 5ns tap value
T =2* intercept, Length=20cm, RMS is show in fig.7,
so (the position resolution) is better than 0.2mm.
(1)
To evaluate the measurement resolution with FEEs and delay line module, lab tests of the whole readout electronics are carry out.
Based on the above analysis, we design a delay line modules with 5ns that can achieve good position resolution. From figure 6 we can get the time different between delay line taps is about 5.5ns, is a little
Bigger than the theory value. And from figure 7, we can get the resolution of time difference with 5ns tap value is better than 550ps. And from expression (1), the position resolution is better than 0.2mm.
joint test with the MWPC detector is also performed, left picture shows the joint test platform, we use 241Am source placed on the detector to simulate neutron hitting is shown in middle picture. The right figure shows the resolution result, which we can conclude the resolution of neutron hit position is better than 2mm.
Joint test with MWPC detector, the position
resolution is better than 2mm.

13. Introduction Design Summary
Frist, introduced the structure of boron-coated MWPC detector.
We know neutron is an ideal probe for studying dynamical properties and the structure of matter.Traditionally, most of the neutron scattering spectrometers adopt (helium 3)3He gas neutron detector. However, in recent years, the shortage of 3He gas brings challenge for the usage of this kind of detector in new applications. In order to solve this problem, we find 10B (boron 10) can absorb neutrons and the reaction process is introduced here. And the reaction products are easy to measure.
So the Institute of High Energy Physics(IHEP) design a two dimensional boron-coated MWPC detector. The structure of the detector is shown on the left. In the detector, the incident window is covered by boron converter, and the secondary particles enter the electric field and cause avalanche near the anode wire. Induced current is extracted from the readout electrode for further processing. And the picture of detector is shown on the right.
The parameters of this detector is described here, the effective area is about 20 centimeter multiply 20 centimeter. The distance from incident window to cathode plane is 8 millimeter and from anode plan to cathode plane is 3 millimeter; The distance between anode wire is 2mm, the diameter of anode wire is 25μm(micrometer)； The distance between cathode wire spacing is 1mm, the diameter of cathode is 50μm.

14. Thank you for your attention
Summary
Time different resolution of TDC can achieve better than 35ps(RMS).
Joint test with MWPC detector, the position resolution (RMS) is better than 2mm.
Thank you for your attention
Figure. 4 shows the structure of TDC, One TDC module can receives 4 channels anode signal and 16 channels cathode signal from four layers of boron-coated MWPC detectors.
And TDC module use coarse and fine time measurement method, Coarse time measurement utilizes a normal binary counter to achieve coarse time, which is a multiple of the clock period. The fine time is measured by interpolation method which is less than one clock period. Fine time measurement utilizes dedicated carry chain resources in the FPGA to construct a delay chain for time interpolation.
To evaluate the time measurement resolution of TDC module. Do some lab tests, the result is show in the figure, Time measurement resolution is better than 35 ps (RMS）