1. Tracker readout, DAQ, C&M and calibration
D Adey
38th MICE Collaboration Meeting
Napa CA
23rd February 2014

2. Content
Readout – Test bench at FNAL, digitisation speeds, global timing correlation
DAQ – Standalone library for tracker DAQ
C&M – Rewrite of controls and monitoring software, EPICS integration, ConfigDB use
Calibration – Diagnostics, time walk
Present at FNAL test bench:
AFE board, VLSB board, LVDS cables, 1553, VME controllers, Power supplies, PCs for linux and windows (temporary)
Acquired one month FTE from ED for assistance, which will include firmware installation help, documentation assistance but not digitisation speed-up

3. Readout of 128 VLPC channel module split between boards
Tracker
VLPC
AFE x 8
VLSB x 8
1 LDC
Photo-conversion
Digitisation
Data buffer
Event building
Waveguides
Connector x 8
AFE
Bias
AFE
Cassette
AFE
Bias
Temp
VLPC x 8
Cryo
VLPC
Readout of 128 VLPC channel module split between boards
Bias of 64 channel half controlled by each board
Temperature of 128 channel module controlled by one board

4. Each 64 channel group of AFE split into two 32 channel groups
Charge collected, integrated, discriminated and time by ASIIC – Trigger, Pipeline and Time (TriPt)
One two channel ADC per TriPt
Digitisation time is 9 clock cycles x 18.8ns cycle x 34 channels = 5.7μs – this is very difficult to alter – time and expertise negligible
Light must arrive in integration period
Triggers must be vetoed to only collect integrated charge
Arrival of particles is asynchronous – integration period derived from ISIS RF cycle
ADC
Discriminator level
TDC
Integration period

6. Tracker absolute timing information
If TDCs are to be used internal TDC time needs to be correlated against “global” trigger time
Concept will be implemented at FNAL test-bench
DAQ additions are relatively simple
Software will need to adapt
Signal

7. Controls
Requires:
Setting bias, temperature, discriminator levels, timing amplifiers, delays and pipeline depths, with associated amplifiers, current sources, reference voltages etc.
Configuration of FPGAs – book-keeping, clock source, charge injection levels, delays maps
Loading of firmware and powering of FPGAs
One bulk programming of O(3000) free parameters over layered interfaces

8. Programming
VME
1553
1553
PIC
FPGA
TriPt
Conceptual order
FPGA
Parameter
PIC
1553
VME
TriPt

9. Configure Bias Turn On Set Bias
Existing C++ C/M infrastructure works by list of functions which perform certain tasks, activity within functions not transparent (nor is even which part of hardware is being dealt with)
Most variables arise from xml files, some are hard-coded. Some are EPICS PVs. Other static commands are hard-coded.
Turn On
Write(0x4,0xCC)
Write(0x24,0x1)
Write(0xF,0xF4)
Write(0x,0x1)
Set Bias
FPGAWrite(Address,Data)
FPGAWrite(0x4,0x1C)
FPGAWrite(0x0,0x1)
FPGAWrite(Address,Bias)
FPGAWrite(0x4,0x1)
Write(0x1,FPGA_ID)
Write(0xC,Address)
Write(0xF,Bias)

10. New concept Parameters Register Map Function List Functions
InitialisationState
Parameters
Convert and store parameters
Retrieve parameters from DB. Retrieve static commands from similar.
Register Map
Function List
Functions
eg. Turn on FPGA
(PIC Command)
Program this state
Programmer
FPGACommands
Turn On
PICCommandList
Form list of commands
Import Firmware
PICCommandList
Set Bias
FPGACommandList

11. Programmer FPGA Programmer PIC Programmer 1553 Programmer VME
Turn On
Turn On
PICCommandList
CommandList
Cast as Base
Import Firmware
PICCommandList
Import Firmware
CommandList
Set Bias
FPGACommandList
Set Bias
CommandList
virtual getType()
Programmer
interfaceProgrammers[type]->program(command)
FPGA
Programmer
PIC
Programmer
1553
Programmer
VME
Programmer
VME
Controller
Wrap as PIC
Commands
Wrap as 1553
Commands
Wrap as VME
Commands

12. Monitoring
Only parameter of interest (and available) from analogue front end is the temperature of the VLPC modules
Tracker CM software will read out temperatures (every spill) and write to EPICS PV which is then archived and alarmed
Cryo temperatures, vacuums, pressures are also of interest but seperate

13. Data acquisition

14. VLSBMasterController
DATE thinks things should be controlled in a specific order – ends up with multiple classes and equipment definition for same hardware
Create DATE-free classes to do low level hardware, which can be called by DATE or run alone
Enable data mode
in VLSB
Start of burst
Event Type
Enable triggering in
VLSB Master
Triggers
Release veto
Disable triggering in
VLSB Master
Physics Event
Event Type
VLSBMasterController
Disable data mode
in VLSB
VLSBController
Readout VLSB
Time
Finish with multiple wrappers but modular code
* VME LVDS SerDes Buffer
VLSB Master fans out triggers to VLSBS
ReadoutEvent
Date C
ReadBank
DATE C++
ReadVLSB
C++

15. Calibrations Temperature – already well defined
Bias – Essential, but well defined and stable – 40 data points
Discriminators – Required for zero-suppression (at readout end). Possibly environment dependant. Source of analogue noise – data points maximum, in reality ~100
TDCs – Required to get time information. Simple calibration. Also environment dependant and source of noise – 10 data points
Time walk – compensate for ADC-TDC correlation – 50 data points
Diagnostics – Take standard data and compare to accepted distributions – weekly, if fail, re-calibrate

16. Calibrate(algorithm)
Runs on highly compressed output of “mini-DAQ”
DATE GDC/LDC also readable
Calibrator
BiasCalibrator
Light Yield
Calibrator
Data set
number
Local DB
Get data files
TimingCalibrator
Time Walk
Calibrator
Calibration
Manager
GainCalibrator
Discriminator
Calibrator
Write time stamped calibration
Add calibrators
Calibrate(algorithm)

17. Several algorithms available for each calibration type – user defined
Bias calibrated by requiring the noise rate to be 2%
e.g. Limits of integration define dark count

18. Equivalency of dark count and efficiency

19. TDC calibration is simple, completed and tested – quicks of the real system have not been fully investigated, but specification of the TriPts is a resolution of 0.5ns
Calibrating temperature away from 9K is also possible, which could impact on the efficiency (T affects quenching and dark count), but code to do this has not been written and is very low priority.

20. Time walk Time above threshold function of total charge deposited
Simulation
Time above threshold function of total charge deposited
Issue only when we use timing
Calibration concept defined, but little developed
Involves varying the discriminator for a known amount of injected charge to characterise the pulse shape over time
Discriminator level Q
Time

21. Automation Goal is to automate initialisation, DAQ and calibration
Manager
Choose
Calibrators,
Algorithms,
Parameter
Range,
Data set
Goal is to automate initialisation, DAQ and calibration
Control of this process conceptually working in python – however CM link is assumed in testing
Currently command line, GUI for user would be preferable
Initialise
Readout
Calibrate

22. Schedule Assuming deadline of end of June
Need for EPICS expertise minimised.
Development required on:
Config DB
GUI
Diagnostics
Linux-based firmware installs
Unit tests
User friendly automation