1. Arria 10 HPS External Memory Interface Guidelines
Quartus Prime Software v17.0

2. Introduction This slide deck covers the following topics:
HPS EMIF limitations/restrictions
HPS EMIF IP generation
HPS EMIF pin constraints
*EMIF = External Memory Interface

3. Software Requirements
Quartus Prime Software v17.0

4. HPS EMIF Overview HPS EMIF supports: HPS EMIF does not support:
Half-rate interfaces
Interface widths of 16, 32, and 64 (without ECC)
Interface widths of 24, 40, and 72 (with ECC)
x8 data groups
DDR3 and DDR4
HPS EMIF does not support:
Ping-Pong PHY
EMIF Debug Toolkit
Quad-rank interfaces
LRDIMM memory formats

5. Creating a Quartus Prime Project
The following slides demonstrate how to create a Quartus Prime project
Starting with Quartus Prime v17.0, users must create a Quartus Prime project before generating the EMIF IP and accompanying example design project
Launch Quartus Prime and select New Project Wizard
Or File > New Project Wizard
Press Next, select a directory and name for the project, and select Next
New Project Wizard
/data/dabdulra/hps_emif_example
hps_emif_example

6. Creating a Quartus Prime Project
Select Empty project and continue to press Next until you reach the Family, Device, and Board Settings option
Select Arria 10 (GX/SX/GT) under Family and then select your specific Arria 10 device under Available devices
You can filter the available devices list using the options on the right, including the Name filter
Press Finish

7. Generating the HPS EMIF IP
The following slides demonstrate how to generate the HPS EMIF IP
For more information on how to do this, refer to slides 6-7
Launch Qsys:
Tools > Qsys
Create a new Qsys system

8. Generating the HPS EMIF IP
Click on the IP Catalog tab in the top-left corner
If the IP Catalog is not visible: View > IP Catalog
Select Processors and Peripherals > Hard Processor Components
Double-click Arria 10 External Memory Interfaces for HPS

9. HPS EMIF Pin Guidelines
The following slides cover pin placement restrictions for HPS EMIF systems
Arria 10 SoC devices have 3 modular I/O banks (2K, 2J, and 2I)
Allows connection to a Hard Processor System (HPS)
For systems using HPS EMIF:
Only Banks 2K, 2J, and 2I can be used
These banks can be used as FPGA GPIO when there is no HPS EMIF in the system
Top bank is reserved for Address/Command pins
Unused lanes can be used as FPGA inputs/outputs
Unused pins in lanes used for data/ECC can be used as FPGA inputs only
Users of SDRAM for HPS must instantiate the HPS EMIF in Qsys
This allows the right banks/lanes to be assigned for the SDRAM I/O

10. HPS EMIF Pin Constraints
Design intent for Bank 2K when using HPS EMIF:
Lane 3 is used for ECC for SDRAM
Unused pins in this lane may be used as FPGA inputs only, regardless whether ECC is enabled
The remaining lanes are used for Address/Command
Unused pins in these lanes (0-2) may be used as FPGA inputs/outputs
Bank 2K
ECC
Address/Command
With/Without ECC
Lane 0
Lane 1
Lane 2
Lane 3
Pins not dedicated for ECC can be used as FPGA inputs only

11. HPS EMIF Pin Constraints
Bank 2J
FPGA GPIO
Data
x16 Interface
Lane 0
Lane 1
Lane 2
Lane 3
Design intent for Bank 2J when using HPS EMIF:
Bank 2J is used for data bits [31:0]
With a 16-bit interface, unused pins in the lanes used for data can be used as FPGA inputs only
Pins in the unused lanes can be used as FPGA inputs/outputs
With a 32-bit interface, unused pins can be used as FPGA inputs only
Specific lanes used for data vary depending on device package
Pins not used for data can be used as FPGA inputs only
Bank 2J
Data
x32 Interface
Lane 0
Lane 1
Lane 2
Lane 3
Pins not used for data can be used as FPGA inputs only

12. HPS EMIF Pin Constraints
Bank 2I
FPGA GPIO
GPIO
x16 or x32 Interface (located in Bank 2J)
Lane 0
Lane 1
Lane 2
Lane 3
Design intent for Bank 2I when using HPS EMIF:
Bank 2I is used for data bits [63:32]
With a 16-bit or 32-bit interface, this bank can be used as FPGA inputs/outputs
With a 64-bit interface, unused pins can be used as FPGA inputs only
Not all devices contain Bank 2I
Bank 2I
Data
x64 Interface
Lane 0
Lane 1
Lane 2
Lane 3
Pins not used for data can be used as FPGA inputs only