1. Arria 10 External Memory Interface Timing Closure Guidelines
Quartus Prime Software v17.0

2. Introduction Quartus Prime performs system-level timing closure
For external memory interfaces, Report DDR is used as the final signoff for timing closure
This slide deck covers the following topics:
Report DDR
EMIF IP parameters
For more information regarding timing, refer to the Analyzing Timing of Memory IP section in the External Memory Interface Handbook
*EMIF = External Memory Interface

3. Software Requirements
Quartus Prime Software v17.0

4. I/Os including read, write, write leveling , etc.
EMIF Timing Paths
Memory
Package Traces
PHY
FPGA Core
P2C
C2P
P2P
C2C
FPGA
User Logic (Core)
Periphery
I/Os including read, write, write leveling , etc.

5. Timing Closure Guidelines
Timing closure involving core transfers includes the following:
Last set of registers in core to first set of registers in periphery (C2P)
Last set of registers in periphery to first set of registers in core (P2C)
Timing closure involving any I/Os is affected by:
Memory
FPGA speed grade parameters
Channel effects
Timing closure regarding I/O transfers is not dependent on Quartus Prime compilation

6. Timing Closure Guidelines
For accurate timing analysis:
Board skews must be simulated using a board simulation tool
Not estimated or calculated via trace length
Channel effects (ISE and crosstalk) must be determined through board simulation
Reflect simulated board skew and channel effects in the IP GUI during IP generation
Refer to the Board Guidelines section for more details on board skew and channel effects
Report DDR Core Timing analysis
Runs automatically as part of timing analysis
Must be checked to “signoff” that EMIF has closed timing
Does not include user logic timing to/from EMIF

7. Report DDR Report DDR is used for Arria 10 EMIF timing analysis
Includes:
I/O timing tables
Core analysis
Within Core
Core to Periphery and Periphery to Core
Acts as final sign off for memory interface timing closure
Must enter accurate parameters in Board tab during EMIF IP generation
After compiling your EMIF design in Quartus Prime
Report DDR can be located in the Compilation Report
TimeQuest Timing Analyzer > Model > Report DDR

8. Report DDR Report DDR is used for Arria 10 EMIF timing analysis
Includes:
I/O timing tables
Core analysis
Within Core
Core to Periphery and Periphery to Core
Acts as final sign off for memory interface timing closure
Must enter accurate parameters in Board tab during EMIF IP generation
After compiling your EMIF design in Quartus Prime
Report DDR can be located in the Compilation Report: TimeQuest Timing Analyzer > Model > Report DDR
If the Compilation Report is not visible: Processing > Compilation Report

9. EMIF IP Generation – Memory Tab
The following slides cover important parameters/tabs in the EMIF IP GUI that affect EMIF timing analysis
In the Memory tab of the EMIF IP GUI, the following parameters affect timing analysis:
Number of DIMMs
More DIMMs typically means more channel uncertainty due to reflection and increased loading
Number of physical ranks per DIMM
Usually leads to increased loading and channel uncertainty

10. EMIF IP Generation – Mem Timing Tab
In the Mem Timing tab, there are many parameters that affect the following:
Read capture time
Write and Write leveling
Users must make sure that the memory timing parameters are accurate for proper timing analysis

11. EMIF IP Generation – Board Tab
Channel uncertainty can be a significant source for margin loss
Customers must run channel simulations and enter accurate ISI/Crosstalk values for their board
Default values should not be used
For more information regarding channel simulation, refer to this wiki page
Intrabus skews affect read capture and write timing analysis
Package skews is a result of non-uniform pin trace lengths inside the device package
This affects system timing for high frequency systems
Accurate values must be entered for package deskew for data groups and the Addr/Cmd bus