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ELEC 418 Advanced Digital Systems Dr. Ron Hayne

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1 ELEC 418 Advanced Digital Systems Dr. Ron Hayne
Processor Design ELEC 418 Advanced Digital Systems Dr. Ron Hayne ELEC 418

2 68HC11 Programming Model Motorola 68HC11 Microcomputer (CISC) 7 A 0
B 8-bit Accumulators A & B D 16-bit Double Accumulator D X Index Register X Y Index Register Y SP Stack Pointer PC Program Counter S X H I N Z V C Condition Code Register 418_09a ELEC 418

3 68HC11 Instruction Set Table
Source Form Operation Boolean Expression Addr. Mode Machine Code Bytes Cycles Op Code Op-erand ABX Add B to X X + 00:B  X INH 3A 1 3 ADDA (opr) Add Memory to A A + M  A A IMM A DIR A EXT A IND,X A IND,Y 8B 9B BB AB 18 AB ii dd hh ll ff ff 22323 23445 CLC Clear Carry Bit 0  C 0C 2 LDX (opr) Load Index Register X M:(M + 1)  X X IMM X DIR CE DE jj kk dd 32 34 418_09a ELEC 418

4 MIPS R2000 Instruction Set Architecture (RISC)
32 General-Purpose Registers (32-bits) 3 Instruction Formats R-format (register) I-format (immediate) J-format (jump) 3 Addressing Modes Immediate Register Base register and signed offset 418_09a ELEC 418

5 MicroMIPS Register writeback Instruction fetch Reg access / decode ALU operation Data access Fig Key elements of the single-cycle MicroMIPS data path. Parhami, Computer Architecture: From Microprocessors to Supercomputers, Oxford University Press, 2005

6 PIC18F452 Programming Model

7 Instructional Processor Design
3 Bus Organization 16 bit Data Path 4 Word Register File 4K Word Memory 8 Function ALU 2 Condition Code Flags 6 Data Instructions 4 Addressing Modes 7 Branch Instructions 418_09a ELEC 418

8 ECE 445 Data Path & Memory Map RJH

9 Data Path Registers & Memory
Program Counter (PC) 12-bit Program Address Subroutine Stack (STACK) 16 x 12-bit Addresses Instruction Register (IR) 16-bit Instructions Register File (REGS) 4 x 16-bit Registers Arithmetic Logic Unit (ALU) 8 Functions (ALU_OP) Flag Register (STATUS) Negative Flag (N) Zero Flag (Z) Memory Data Register (MDR) 16-bits to/from Memory Memory Address Reg (MAR) 12-bit Memory Address MEMORY 4K x 16-bit Memory 418_09a

10 Memory Map 4K (4096) RAM 8 Memory-mapped I/O Ports
0x000 Switch (Input) 0x001 LED (Output) 120 Data Memory Locations 0x x07F 3968 Program Memory Locations 0x xFFF 418_09a ELEC 418

11 Addressing Modes Method of specifying of an operand
Immediate (Literal) addressing The operand is a number that follows the opcode Direct (Absolute) addressing The address of the operand is a part of the instruction Indirect addressing An address is specified in a register (pointer) and the MPU looks up the address in that register 418_09a

12 Data Instruction Format
ECE 445 Data Instruction Format IR OP SRC DST VALUE MODE REG # Name Syntax Effective Address SRC or DST 00 00-11 Register Direct Rn EA = Rn 01 Register Indirect [Rn] EA = (Rn) 10 VV Absolute [Value] EA = Value 11* Immediate Value Operand = Value EA = Effective Address VV = Upper 2 bits of VALUE * = SRC only 418_09a RJH

13 Data Instructions OP Inst Assembly Language Register Transfer Notation
ECE 445 Data Instructions OP Inst Assembly Language Register Transfer Notation 000 MOVE MOVE SRC,DST DST <= SRC 001 ADD ADD SRC,DST DST <= SRC + DST 010 INV INV SRC,DST DST <= not SRC 011 AND AND SRC,DST DST <= SRC and DST 100 SHL SHL SRC,DST DST <= SRC(14 downto 0) & 0 101 ASHR ASHR SRC,DST DST <= SRC(15) & SRC(15 downto 1) 110 ... 418_09a RJH

14 Branch Instruction Format
ECE 445 Branch Instruction Format IR OP FN OFFSET OP FN Inst Assembly Language Register Transfer Notation 111 000 BRA BRA Offset PC <= PC + Offset 001 BZ BZ Offset if Z = 1 then PC <= PC + Offset 010 BNZ BNZ Offset if Z = 0 then PC <= PC + Offset 011 BN BN Offset if N = 1 then PC <= PC + Offset 100 BNN BNN Offset if N = 0 then PC <= PC + Offset 101 ... 110 BSR BSR Offset STACK <= PC; PC <= PC + Offset RTN PC <= STACK 418_09a RJH

15 Assembly Language Program
ECE 445 Assembly Language Program program.asm program.bin .data SUM N 3 X 7, -8, 10 .program START: MOVE [N],R1 MOVE X,R2 MOVE 0,R0 LOOP: ADD [R2],R0 ADD 1,R2 ADD -1,R1 BNZ LOOP MOVE R0,[SUM] STOP: BRA STOP MEMORY . . . 008 SUM 009 3 N 00A 7 X(0) 00B -8 X(1) 00C 10 X(2) 418_09a RJH

16 Machine Code 418_09a

17 Details of the Data Path
REG4: 4 x 16-bit Register File MEM4K: 4K x 16-bit Main Memory 418_09a

18 ECE 445 ALU Multiplexers 418_09a © 2018 Cengage Learning®.

19 Arithmetic Logic Unit ALU16 418_09a

20 Control Unit Organization
ECE 445 Control Unit Organization 418_09a RJH

21 Control Signals BUS_A BUS_B REGS_Read1 REGS_Read2 Extend Address
ALU_Op MEM_Read MEM_Write Inc_PC Load_PC Load_IR REGS_Write Load_STATUS Load_MDR Load_MAR Clear 418_09a ELEC 418

22 Control Unit Design Instruction Fetch Cycle Step Register Transfers
Control Signals T0 MAR <= PC PC <= PC + 1 BUS_B <= PC; ALU_OP <= Pass_B; Load_MAR <= ‘1’; Inc_PC <= ‘1’; T1 MDR <= MEMORY(MAR) MEM_Read <= ‘1’; Load_MDR <= ‘1’; T2 IR <= MDR BUS_B <= MDR; Load_IR <= ‘1’; 418_09a ELEC 418

23 Control Unit Design Instruction Execution Cycles MOVE Value,Rd
Immediate (M3), Register Direct (M0) Step Register Transfers Control Signals T3 Rd <= Value BUS_A <= IR; Extend <= ‘1’; ALU_OP <= OP; Load_STATUS <= ‘1’; REGS_Write <= ‘1’; Clear <= ‘1’; 418_09a ELEC 418

24 Control Unit Design MOVE Rs,[Value]
Register Direct (M0), Absolute (M2) Step Register Transfers Control Signals T3 MDR <= Rs REGS_Read1 <= ‘1’; ALU_OP <= OP; Load_STATUS <= ‘1’; Load_MDR <= ‘1’; T4 MAR <= Value BUS_B <= IR; Address <= ‘1’; ALU_OP <= Pass_B; Load_MAR <= ‘1’; T5 MEMORY(MAR) <= MDR MEM_Write <= ‘1’; Clear <= ‘1’; 418_09a ELEC 418

25 Control Unit Design ADD Value,Rd Immediate (M3), Register Direct (M0)
Step Register Transfers Control Signals T3 Rd <= Value + Rd BUS_A <= IR; Extend <= ‘1’; REGS_Read2 <= ‘1’; ALU_OP <= OP; Load_STATUS <= ‘1’; REGS_Write <= ‘1’; Clear <= ‘1’; 418_09a ELEC 418

26 Control Unit Design ADD [Rs],Rd
Register Indirect (M1), Register Direct (M0) Step Register Transfers Control Signals T3 MAR <= Rs REGS_Read1 <= ‘1’; ALU_OP <= Pass_A; Load_MAR <= ‘1’; T4 MDR <= MEMORY(MAR) MEM_Read <= ‘1’; Load_MDR <= ‘1’; T5 Rd <= MDR + Rd BUS_A <= MDR; REGS_Read2 <= ‘1’; ALU_OP <= OP; Load_STATUS <= ‘1’; REGS_Write <= ‘1’; Clear <= ‘1’; 418_09a ELEC 418

27 Control Unit Design BNZ Offset Branch if not zero OP (111), Mode (010)
Step Register Transfers Control Signals T3 if Z = 0 then PC <= PC + Offset BUS_A <= IR; BUS_B <= PC; Extend <= ‘1’; ALU_OP <= ADD; Clear <= ‘1’; if Z = ‘0’ then Load_PC <= ‘1’; 418_09a ELEC 418

28 VHDL Model Data Path Control Unit Test Program Components
Registers & Buses Control Unit Instruction Fetch Instruction Execute Test Program program.asm program.bin .data SUM N 3 X 7, -8, 10 .program START: MOVE [N],R1 MOVE X,R2 MOVE 0,R0 LOOP: ADD [R2],R0 ADD 1,R2 ADD -1,R1 BNZ LOOP MOVE R0,[SUM] STOP: BRA STOP 418_09a Chapter 9a

29 VHDL Model Processor_Components.vhd Processor.vhd Processor_Test.vhd
REG4 ALU16 MEM4K Processor.vhd Data Path Control Unit Processor_Test.vhd 418_09a Chapter 9a

30 Assembly Language Program
ECE 445 Assembly Language Program program.asm program.bin .data SUM N 3 X 7, -8, 10 .program START: MOVE [N],R1 MOVE X,R2 MOVE 0,R0 LOOP: ADD [R2],R0 ADD 1,R2 ADD -1,R1 BNZ LOOP MOVE R0,[SUM] STOP: BRA STOP MEMORY . . . 008 SUM 009 3 N 00A 7 X(0) 00B -8 X(1) 00C 10 X(2) 418_09a RJH

31 Machine Code 418_09a

32 VHDL Simulation (Part 1)
ELEC 418

33 VHDL Simulation (Part 2)
ELEC 418

34 Microcontroller Extension
4K (4096) RAM 8 Memory-mapped I/O Ports 0x000 SWITCH (Input) 8-bit 0x001 LED (Output) 8-bit 0x002 ANODE (Output) 4-bit 0x003 CATHODE (Output) 8-bit 0x004 JA (Output) 4-bit 0x005 JB (Input) 4-bit 120 Data Memory Locations 0x x07F 418_09a ELEC 418

35 FPGA Implementation JA JB Clock Processor LED Reset SWITCH
ANODE/CATHODE 418_09a ELEC 418

36 Memory-mapped I/O Ports
MEM4K (modifications) SWITCH: in std_logic_vector(7 downto 0); LED: out std_logic_vector(7 downto 0); ANODE: out std_logic_vector(3 downto 0); CATHODE: out std_logic_vector(7 downto 0); JA: out std_logic_vector(4 downto 1); JB: in std_logic_vector(4 downto 1)); signal MEM4K:RAM4K:=InitRamFromFile("program_pwm.bin"); signal Buff_Out: std_logic_vector(15 downto 0); Buff_Out <= MEM4K(conv_integer(Addr)); -- synch read 418_09a ELEC 418

37 Memory-mapped Output Ports
if MEM_Write = '1' then -- Memory Mapped Output Ports if Addr = X"001" then -- LED LED <= Data_In(7 downto 0); elsif Addr = X"002" then -- ANODE ANODE <= Data_In(3 downto 0); elsif Addr = X"003" then -- CATHODE CATHODE <= Data_In(7 downto 0); elsif Addr = X"004" then -- JA JA <= Data_In(3 downto 0); end if; 418_09a

38 Memory-mapped Input Ports
-- Memory Mapped Input Ports Data_Out <= (X"00" & SWITCH) when (Addr = X"000" and MEM_Read = '1') -- SW else (X"000" & JB) when (Addr = X"005" and MEM_Read = '1') -- JB else Buff_Out; -- RAM 418_09a

39 Pulse Width Modulation
program_pwm.asm 418_09a

40 IP Assembler Requires Java (jre8) Run from Command Prompt 418_09a

41 Summary Example Microprocessors Instructional Processor Design
Registers and Memory Instructions and Addressing Modes Instructional Processor Design Instruction Set Architecture Data Path Control Unit VHDL Model iSim Simulation FPGA Implementation 418_09a ELEC 418

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