1. Week #7 Sequential Circuits (Part B)
ENG241 Digital Design
Week #7
Sequential Circuits (Part B)
School of Engineering

2. Week #7 Topics Sequential Circuit Analysis Sequential Circuit Design
Designing with D Flip-Flops
Designing with JK Flip-Flops
Designing with T Flip-Flops
VHDL Representations
Examples
School of Engineering

3. Resources Chapter #6, Mano Sections 6.4 Sequential Circuit Analysis
6.5 Sequential Circuit Design
6.7 VHDL Representation of Sequential circuits
School of Engineering

4. Analysis of Sequential Circuits
Earlier we learned how to analyze combinational circuits
We will extend analysis to synchronous sequential
We’ll use
State tables and
State diagrams

5. Review: Flip Flops

6. Analysis of Sequential Circuits
The behavior of a sequential circuit is determined from:
Inputs,
Outputs,
Present state of the circuit.
The analysis of a sequential circuit consists of:
Obtaining a suitable description that demonstrates the time sequence of inputs, outputs and states (STATE DIAGRAM).

7. Step #1: Derive Input Equations
Can describe inputs to FF with logic equations

8. Another Example

9. Input Equations The input equations
Imply the type of flip-flop from the letter symbols,
Fully specify the combinational circuit that drives the flip-flops.

10. Time is Implied Note that previous circuit used the
Present state (A, B, ..) to determine next state
State and inputs to determine output
Synchronous circuit
When are transitions?

11. Step #2: State Table Similar to truth table with state added
A sequential circuit with `m’ FFs and `n’ inputs needs 2m+n rows in state table.
Next State and output are determined using? (input equations)

12. Step#3: State Diagram “Mealy Model”
Input
Output
An alternative representation to State Table
Input/Output

13. Sequential Circuit Types
Moore model – outputs depend on states only.
Mealy model – outputs depend on inputs & states

14. State Diagram: Moore Alternative representation for state table Inputs
State/Output

15. Moore vs. Mealy Machine Moore Machine: Mealy Machine:
Easy to understand and easy to code.
Might requires more states (thus more hardware).
Mealy Machine:
More complex since outputs are a function of both the state and input.
Requires less states in most cases, therefore less components.
Choice of a model depends on the application and personal preference.
You can transform a Mealy Machine to a Moore Machine and vice versa.

16. State Table vs. Diagram Provides same information
Table is perhaps easier to fill in from description
Diagram is easier for understanding and writing code
Analysis for sequential circuits that employs D flip flops is easy. Why?
Because the next state values are obtained directly from the input equations.

17. Analysis with JK Flip Flops
For circuits with other types of flip flops such as JK, the next state values are obtained by following the two step procedure:
Obtain the binary values of each flip-flop input equation in terms of the present state and input variables.
Use the corresponding flip-flop characteristic table to determine the next state.

18. Analysis with JK Flip Flops
JA = B
JB = x’
KA = Bx’
KB = A’x + Ax’ = A  x

19. JK Analysis: State Table
Use the Input equations to determine the FF inputs.
Use the FF inputs and Table to determine the next state.
Flip Flop Inputs
JK Characteristic Table
JA = B
KA = Bx’
JB = x’
KB = A’x + Ax’ = A  x

20. JK Analysis State Table
Flip Flop Inputs
JA = B
JB = x’
KA = Bx’
KB = A’x + Ax’ = A  x

21. JK Analysis: State Diagram1 1 00 11 01 10 1 1

22. Analysis vs. Design
The analysis of sequential circuits starts from a circuit diagram and culminates in a state table or state diagram.
The design of a sequential circuit starts from a set of specifications and we should obtain the state diagram and finally the logic diagram.

23. Design Procedure
Design starts from a specification and results in a logic diagram or a list of Boolean functions.
The steps to be followed are:
Derive a state diagram
Reduce the number of states
Assign binary values to the states
Obtain the binary coded state table
Choose the type of flip flops to be used
Use Excitation Tables to derive state table
Derive the simplified flip flop input equations and output equations
Draw the logic diagram

24. Sequential Circuit Design
Remember that a synchronous sequential circuit is made up of flip flops and combinational gates.
Part of the design is to choose the flip-flop type and combinational circuit structure which, together with the flip-flops produce a circuit that fulfills the stated specification.
How many FLIP FLOPS?
The number of flip-flops is determined from the number of states in the circuit
n flip-flops can represent up to 2n binary states.
Examples:
2 states requires a single Flip Flop
4 states requires two flip flops
8 states requires three flip flops
7 states requires again three flip flops …

25. Designing with D Flip-Flops
Design a clocked sequential circuit that operates according to the state diagram. Use
D Flip Flops

26. Synthesizing Using D Flip Flops
The next step is to create a state table and then select two D flip flops to represent the four states, labeling their outputs as A and B.
There is one input, x, and one output, y, representing the input sequence and the output value respectively.
Remember that the Excitation Table (characteristic equation) of the D flip flop is
Q(t + 1) = DQ
This means that the next-state values in the state table specify the D input condition for the flip flop.

27. Designing with D Flip-Flops
Input equations can be obtained directly from the table using minterms:
A(t + 1) = DA(A, B, x) = ∑m(2,4,5,6)
B(t + 1) = DB(A, B, x) = ∑m(1,3,5,6)

28. Designing with D Flip-Flops
However, we have to minimize the expression in a similar way used for combinational logic design!

29. Designing with D Flip-Flops

30. Designing with D Flip-Flops
DA = AB’ + BX’
DB= A’X + B’X+ ABX’
Y = B’X

31. A Sequence Detector
Design a circuit that detects a sequence of three ones. Use Moore Machine.
Create the state diagram
Input
Circuit Detects
`111’ at input
Output
Moore Machine

32. Synthesizing Using D Flip Flops
The next step is to create a state table and then select two D flip flops to represent the four states, labeling their outputs as A and B.
There is one input, x, and one output, y, representing the input sequence and the output value respectively.
The output y is `1’ only when we detect the input sequence of `111’

33. State Table for Sequence Detector
Input equations can be obtained directly from the table using minterms:
A(t + 1) = DA(A, B, x) = ∑m(3, 5, 7)
B(t + 1) = DB(A, B, x) = ∑m(1, 5, 7)
y(A, B, x) = ∑m(6, 7)

34. Boolean Minimization
K-Maps can be used to minimize the input equations, resulting in
DA = Ax + Bx
DB = Ax + B’x
Y = AB

35. Logic Diagram of Sequence Detector

36. Sequential Circuits with different Flip Flops (JK, T)
The design of sequential circuits other than D type flip flops is complicated by the fact that input equations must be derived indirectly from the state table.
It is necessary to derive a functional relationship between the state table and the input equations.

37. Excitation Table
During the design, we usually know the transition from present to next state but we need to find the flip flop input conditions that will cause the required transition.
We need a table that lists the required inputs for a given change of state, called an excitation table.

38. Excitation Tables Characteristic Table Excitation Table

39. Synthesis Using JK Flip Flops
Synthesis of circuits with JK flip flops is the same as with D flip flops
Except that the input equations must be evaluated from the present-state to the next-state transition derived from the excitation table.

40. Example: JK Synthesis Step #1: Obtain State Table Example: No output
Example: No output 00 1 1 1 01 11 1 10

41. JK Synthesis: State Table
Present
State
Next
State 1 1

42. Cont .. Example JK Synthesis
Step #2: Use K-Maps

43. Cont .. Example JK SynthesisBx 00 01 11 10 A 1
JA = BX’ 1 X X X X

44. Cont .. Example JK Synthesis

45. Cont .. JK Synthesis Logic Diagram

46. Synthesis Using T Flip Flops
Synthesis of circuits with T flip flops is the same as with JK flip flops … except that the input equations must be evaluated from the present-state to the next-state transition derived from the T excitation table.

47. Synthesis Using T Flip Flops
Design a counter that counts from “000” to “111” and then back to “000” again.
Constraint: Use T Flip-Flops

48. A Counter using T Flip Flops
000
001
010
011
111
110
101
100
Notice the only input is the clock!

49. Example: T Flip Flop Synthesis

50. Cont .. T Flip Flops
By using K-maps we can minimize the flip flop input equations. T 1 A0 A1 A2

51. One Dimensional Tables

52. Two Dimensional Tables
Same thing, different layout

53. Example – Sequence Recognizer (VHDL)
Circuit has input: W and output: Z
Recognizes sequence of 11 on W
Specifically, if W has been 1 and next bit is 1, make Z high
Design a Moore and Mealy Machines
Sequence
Recognizer W Z

54. Sequence Recognizer (Mealy)
Reset
w=1/z=0 A B
w=0/z=0
w=0/z=0
w=1/z=1
Clk: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
t10 w: 1 z:

55. Mealy: ImplementationB
w=1/z=0
w=0/z=0
Reset
w=1/z=1
Clk: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
t10 w: 1 z:

56. Reset w=1/z=0 A B w=0/z=0 w=1/z=1 School of Engineering
-- (Mealy Machine of Sequence Recognizer)
library IEEE;
use IEEE.std_logic_1164.all;
entity SeqRec_Mealy is
port (reset, clk, w: in std_logic;
z: out std_logic);
end entity SeqRec_Mealy;
architecture behavioral of SeqRec_Mealy is
type statetype is (A, B); -- define new type
signal present_state, next_state: statetype;
Begin
clk_process: process(reset,clk)
begin
if reset = ‘1’ then Check for reset and initialize state
present_state <= A;
Elsif (rising_edge(clk)) then wait until the rising edge
present_state <= next_state;
end if;
end process clk_process;
end architecture behavioral;
next_out_process: process(present_state,w) is
begin
case present_state is depending upon current state
when A => set output signals and next state
if w = '0' then
next_state <= A;
z <= ‘0';
else
next_state <= B;
z <= '0';
end if;
when B =>
if w = '1' then
z <= ‘1';
end case;
end process next_out_process; A B
w=1/z=0
w=0/z=0
Reset
w=1/z=1
School of Engineering

57. Sequence Recognizer (Moore)
Reset
w=1
A/z=0
B/Z=0
w=0
w=0
w=1
w=0
C/z=1
w=1
Clk: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
t10 w: 1 z:

58. Moore: Implementation
A/z=0
B/Z=0
C/z=1
w=1
w=0
Reset
Clk: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
t10 w: 1 z:

59. Reset w=1 w=0 w=0 w=0 w=1 w=1 School of Engineering
next_state_process: process( present_state, w) is
begin
case present_state is depending upon current state
when A => set next state
if w = '0' then
next_state <= A;
else
next_state <= B;
end if;
when B =>
if w = ‘0' then
next_state <= C;
when C =>
if w = ‘0’ then
end case;
end process next_state_process;
-- (Moore Machine of Sequence Recognizer)
library IEEE;
use IEEE.std_logic_1164.all;
entity SeqRec_Moore is
port (reset, clk, w: in std_logic;
z: out std_logic);
end entity SeqRec_Moore;
architecture behavioral of SeqRec_Moore is
type statetype is (A, B,C); -- define new type
signal present_state, next_state: statetype;
Begin
clk_process: process( reset, clk)
begin
if reset = ‘1’ then Check for reset and initialize state
present_state <= A;
Elsif (rising_edge(clk)) then wait until the rising edge
present_state <= next_state;
end if;
end process clk_process;
output_process: process( present_state) is
begin
case present_state is depending upon current state
when A => set output signals
z<= ‘0’;
when B =>
when C =>
z<= ‘1’;
end case;
end process output_process;
End architecture behavioral,
Reset
w=1
A/z=0
B/Z=0
w=0
w=0
w=0
w=1
C/z=1
w=1
School of Engineering

60. End Slides

61. T Flip Flop Analysis
Analysis of a sequential circuit with T flip flops follows the same procedure outlined for JK flip flops.
The next state values in the state table can be obtained by using the characteristic table or the characteristic equation
Q(t + 1) = T  Q = T’Q + TQ’

62. T Flip Flop Analysis ExampleB R x
CLK
Reset
TA = Bx
TB = x
Y = AB

63. T Flip Flop Analysis State Table
TA = Bx
TB = x
Y = AB
A(t + 1) = TA  A = Bx  A
B(t + 1) = TB  B = x  B