1. Designing Combinational Logic Circuits in Verilog - 1
Discussion 7.1

2. Designing Combinational Logic Circuits in Verilog - 1
Gates
Multiplexers
Adder
Subtractor

3. Hardware Description Languages
Verilog
ABEL
VHDL
We will only cover Verilog
VHDL is taught in CSE 378

4. Verilog

5. Verilog source code gates.v
module gates(x,y,invx,invy,andd,orr,nandd,norr,xorr,xnorr);
input x;
input y;
output invx;
output invy;
output andd;
output orr;
output nandd;
output norr;
output xorr;
output xnorr;
assign invx = ~x;
assign invy = ~y;
assign andd = x & y;
assign orr = x | y;
assign nandd = ~(x & y);
assign norr = ~(x | y);
assign xorr = x ^ y;
assign xnorr = x ~^ y;
endmodule

6. Pin numbers set it separate file: gates.ucf
NET "x" LOC = "p11";
NET "y" LOC = "p7";
NET "invx" LOC = "p35";
NET "invy" LOC = "p36";
NET "andd" LOC = "p37";
NET "nandd" LOC = "p39";
NET "orr" LOC = "p40";
NET "norr" LOC = "p41";
NET "xorr" LOC = "p43";
NET "xnorr" LOC = "p44";

7. Gates.v Verilog gate level primitives Verilog reduction operators
module gates ( X ,Z, Y );
input [4:1] X ;
wire [4:1] X ;
output [6:1] Z ;
wire [6:1] Z ;
output [6:1] Y ;
wire [6:1] Y ;
and(Z[6],X[1],X[2],X[3],X[4]);
nand(Z[5],X[1],X[2],X[3],X[4]);
or(Z[4],X[1],X[2],X[3],X[4]);
nor(Z[3],X[1],X[2],X[3],X[4]);
xor(Z[2],X[1],X[2],X[3],X[4]);
xnor(Z[1],X[1],X[2],X[3],X[4]);
assign Y[6] = &X;
assign Y[5] = ~&X;
assign Y[4] = |X;
assign Y[3] = ~|X;
assign Y[2] = ^X;
assign Y[1] = ~^X;
endmodule
Verilog gate level primitives
Verilog reduction operators

8. and(Z[6],X[1],...
nand(Z[5],X[1], ...
or(Z[4],X[1], ...
nor(Z[3],X[1], ...
xor(Z[2],X[1], ...
xnor(Z[1],X[1], ...
assign Y[6] = &X;
assign Y[5] = ~&X;
assign Y[4] = |X;
assign Y[3] = ~|X;
assign Y[2] = ^X;
assign Y[1] = ~^X;

9. Implementing Combinational Logic Circuits in Verilog
Gates
Multiplexers
Adder
Subtractor

10. Multiplexers s1 s0 C0 C1 4 x 1 MUX Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2

11. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
A multiplexer is a
digital switch
0 0

12. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
0 1

13. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
1 0

14. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
1 1

15. A 2 x 1 MUX
Z = A & ~s0 | B & s0

16. A 4 x 1 MUX A = ~s0 & C0 | s0 & C1 B = ~s0 & C2 | s0 & C3
Z = ~s1 & A | s1 & B
Z = ~s1 & (~s0 & C0 | s0 & C1)
| s1 & (~s0 & C2 | s0 & C3)

17. A 4 x 1 MUX Z = ~s1 & (~s0 & C0 | s0 & C1) | s1 & (~s0 & C2 | s0 & C3)

18. A 4 x 1 MUX case(s) 2'b00 : Z = C0; 2'b01 : Z = C1; 2'b10 : Z = C2;
default: Z = C0;
endcase

19. Problem How would you make a Quad 2-to-1 MUX?s
0 A
1 B
Quad
2-to-1
MUX
[A3..A0]
[Y3..Y0]
[B3..B0] s

20. mux.v [A3..A0] [Y3..Y0] [B3..B0] s Quad 2-to-1 MUX
module mux24(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
wire [3:0] Y;
assign Y = {4{~s}} & A | {4{s}} & B;
endmodule
Quad
2-to-1
MUX
[A3..A0]
[Y3..Y0]
[B3..B0] s

21. module mux24(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
wire [3:0] Y;
assign Y = {4{~s}} & A | {4{s}} & B;
endmodule

22. mux.v [A3..A0] [Y3..Y0] [B3..B0] s Quad 2-to-1 MUX
module mux24a(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
reg [3:0] Y;
if(s == 0)
Y = A;
else
Y = B;
endmodule
Quad
2-to-1
MUX
[A3..A0]
[Y3..Y0]
[B3..B0] s

23. module mux24a(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
reg [3:0] Y;
if(s == 0)
Y = A;
else
Y = B;
endmodule

24. mux.v [A3..A0] [Y3..Y0] [B3..B0] s Quad 2-to-1 MUX
module mux24(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
wire [3:0] Y;
assign Y = s ? B : A;
endmodule
Quad
2-to-1
MUX
[A3..A0]
[Y3..Y0]
[B3..B0] s

25. Implementing Combinational Logic Circuits in Verilog
Gates
Multiplexers
Adder
Subtractor

26. Half Adder 1 1 +1 +1 2 10 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Dec Binary AB S C 1 A B S C 1
Dec Binary
1 1
+1 +1
2 10

27. Multiple-bit Addition
A3 A2 A1 A0
B3 B2 B1 B0 A B
Ci+1
+Ci 1 1 1 A Ai
+Bi B Si 1 1

28. Full Adder Si Ci Ai Bi Si Ci+1 Ci AiBi 00 01 11 10 1 0 0 0 0 01 Si 1 1 1 1

29. Full Adder Ci Ai Bi Si Ci+1 Si = ~Ci & ~Ai & Bi | ~Ci & Ai & ~Bi

30. Full Adder Si = ~Ci & ~Ai & Bi | ~Ci & Ai & ~Bi | Ci & ~Ai & ~Bi
Si = ~Ci & (~Ai & Bi | Ai & ~Bi)
| Ci & (~Ai & ~Bi | Ai & Bi)
Si = ~Ci & (Ai ^ Bi)
| Ci & (Ai ~^ Bi)
Si = Ci ^ (Ai ^ Bi)

31. Full Adder Ci+1 Ci Ai Bi Si Ci+1 Ci AiBi 00 01 11 10 1 0 0 0 0 01
Ci+1 1 1 1 1

32. Full Adder Ci+1 Ci AiBi 00 01 11 10 1 Ci Ai Bi Si Ci+1 0 0 0 0 01
Ci Ai Bi Si Ci+1 1 1 1 1
Ci+1
Ci+1 = Ai & Bi
| Ci & Bi
| Ci & Ai

33. Full Adder Ci+1 Ci AiBi 00 01 11 10 1 Ci Ai Bi Si Ci+1 0 0 0 0 01
Ci Ai Bi Si Ci+1 1 1 1 1
Ci+1
Ci+1 = Ai & Bi
| Ci & ~Ai & Bi
| Ci & Ai & ~Bi

34. Full Adder Recall: Ci+1 = Ai & Bi | Ci & ~Ai & Bi | Ci & Ai & ~Bi
| Ci & (~Ai & Bi | Ai & ~Bi)
Ci+1 = Ai & Bi | Ci & (Ai ^ Bi)
Recall:
Si = Ci ^ (Ai ^ Bi)
Ci+1 = Ai & Bi | Ci & (Ai ^ Bi)

35. Full Adder Half-adder Si = Ci ^ (Ai ^ Bi)
Ci+1 = Ai & Bi | Ci & (Ai ^ Bi)
Half-adder

36. Full Adder A full adder can be made from
two half adders (plus an OR gate).

37. Full Adder
Block Diagram

38. 4-Bit Adder C A B S

39. adder4.v module adder4(A,B,S,Cout); input [3:0] A; input [3:0] B;
output [3:0] S;
output Cout;
wire [3:0] S;
wire [4:0] C;
assign C[0] = 0; // zero carry in
assign S = A ^ B ^ C[3:0];
assign C[4:1] = A & B | (A ^ B) & C[3:0];
assign Cout = C[4];
endmodule

40. adder4.v module adder4(A,B,S); input [3:0] A; input [3:0] B;
output [3:0] S;
reg [3:0] S; B)
begin
S = A + B;
end
endmodule

41. 4-Bit Adder C
0:A
0:B
C4:S

42. adder.v module adder4(A,B,S,carry); input [3:0] A; input [3:0] B;
output [3:0] S;
output carry;
reg [3:0] S;
reg carry;
reg [4:0] temp; B)
begin
temp = {1'b0,A} + {1'b0,B};
S = temp[3:0];
carry = temp[4];
end
endmodule
Note: In the sensitivity list a comma can be used in place of or in Verilog 2001
Concatenate a leading 0

43. 4-Bit Adder

44. Implementing Combinational Logic Circuits in Verilog
Gates
Multiplexers
Adder
Subtractor

45. Half Subtractor 2 1 -1 1 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 A D B C A B DB D C 1 1 2 1 -1 1

46. Multiple-bit Subtraction
A3 A2 A1 A0
B3 B2 B1 B0 A B
Ci+1
- Ci 1 1 A Ai
- Bi B Di 1 1 1 1

47. Full Subtractor Di Same as Si in full adder Ci Ai Bi Di Ci+1 Ci AiBi00 01 11 10 1 1 1 1 1 Di
Di = Ci ^ (Ai ^ Bi)
Same as Si in full adder

48. Full Subtractor Ci+1 Ci AiBi 00 01 11 10 1 Ci Ai Bi Di Ci+1 0 0 0 0 01
Ci Ai Bi Di Ci+1 1 1 1 1
Ci+1
Ci+1 = ~Ai & Bi
| Ci & ~Ai & ~Bi
| Ci & Ai & Bi

49. Full Subtractor Recall: Ci+1 = ~Ai & Bi | Ci & ~Ai & ~Bi
| Ci & (~Ai & ~Bi | Ai & Bi)
Ci+1 = ~Ai & Bi | Ci & ~(Ai ^ Bi)
Recall:
Di = Ci ^ (Ai ^ Bi)
Ci+1 = ~Ai & Bi | Ci & ~(Ai ^ Bi)

50. Full Subtractor half subtractor Di = Ci ^ (Ai ^ Bi)
Ci+1 = ~Ai & Bi | Ci & ~(Ai ^ Bi)
half subtractor

51. sub4.v module sub4(A,B,D,Cout); input [3:0] A; input [3:0] B;
output [3:0] D;
output Cout;
wire [3:0] D;
wire [4:0] C;
assign C[0] = 0; // zero borrow in
assign D = A ^ B ^ C[3:0];
assign C[4:1] = ~A & B | ~(A ^ B) & C[3:0];
assign Cout = C[4];
endmodule

52. sub4.v module sub4(A,B,D); input [3:0] A; input [3:0] B;
output [3:0] D;
reg [3:0] D; B)
begin
D = A - B;
end
endmodule

53. Adder/Subtractor

54. Reordered Full Adder Full Subtractor Full Adder 0 0 0 0 0 0 0 1 1 1
Ci Ai Bi Di Ci+1
Full
Subtractor
Full Adder
Ci Ai Bi Si Ci+1
Ci Ai Bi Si Ci+1
NOT

55. Making a full subtractor from a full adder

56. Adder/Subtractor
E = 0: 4-bit adder
E = 1: 4-bit subtractor

57. 4-bit Subtractor: E = 1 +1 Add A to !B (one’s complement) plus 1
That is, add A to two’s complement of B
D = A - B