Introduction to Programmable Logic Devices

Introduction to Programmable Logic Devices
5/10/2018 Introduction to Programmable Logic Devices Edward Freeman STFC Technology Department Detector & Electronics Division

PPD Lectures 5/10/2018 Programmable Logic is a Key Underlying Technology for PP Experiments. First-Level and High-Level Triggering Data Transport (Networks) Computers interacting with Hardware (Networks) Silicon Trackers (Millions of Data Channels) Commercial Devices. Developments driven by Industry. Telecomms, Gaming, Aerospace, Automotive, Set-top boxes…. ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Particle Physics Electronics
5/10/2018 Particle Physics Electronics CMS Custom Electronics Chips ASICs ANALOGUE $$$ Rad Hard, Low Power CERN LHC ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

5/10/2018 Particle Physics Electronics CMS Custom Electronics Chips ASICs ANALOGUE $$$ Rad Hard, Low Power CERN LHC ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Electronics Rooms Trigger Systems. DAQ Systems. DIGITAL Custom Digital Processing Boards VME Bus Crates

5/10/2018 Special Dedicated Logic Functions (not possible in CPUs) Ultra Fast Trigger Systems (Trigger Algorithms) Clock Accurate Timing Massively Parallel Data Processing (Silicon Trackers with Millions of Channels) Custom Designed Printed Circuit Boards PCBs. ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Commercial Programmable Logic Devices, FPGAs

CMS DAQ/Trigger Architectures
5/10/2018 CMS Fully custom PP ASICs Programmable Logic DIGITAL CPUs Commodity PCs ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time “Telecoms Network” ~ 1 Tbps

Lecture Outline FPGA Field Programmable Gate Array
5/10/2018 Programmable Logic Devices Basics Evolution FPGA Field Programmable Gate Array Architecture Design Flow Hardware Description Languages Design Tools ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Digital Logic Logic Gates 5/10/2018 ‘outline’ of coverage time-plan
- What is an FPGA - And why are they important for HEP questions - any time

Digital Logic Logic Gates Transistor Switches 5/10/2018
‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Transistor Switches

Digital Logic < 40 nm ! $$$ Logic Gates MOORE’S LAW
5/10/2018 Logic Gates MOORE’S LAW ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Transistor Switches < 40 nm ! $$$

Digital Logic Digital Logic Function Product AND (&) Sum OR (|)
5/10/2018 Digital Logic Function Product AND (&) Sum OR (|) 3 Inputs SUM of PRODUCTS Black Box Truth Table (Look Up Table LUT) ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Digital Logic Black Box SUM of PRODUCTS Truth Table
5/10/2018 Black Box SUM of PRODUCTS Truth Table (Look Up Table LUT) Digital Logic Function 3 Inputs Product AND (&) Sum OR (|) ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Programmable Logic Devices PLDs
5/10/2018 Inputs SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC Un-programmed State ANDs Planes of ANDs, ORs ORs Outputs Logic Functions ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

5/10/2018 Inputs SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC Un-programmed State ANDs Planes of ANDs, ORs ORs Outputs Logic Functions Sums ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Programmed PLD Product Terms

5/10/2018 Logic Functions Programmed PLD Sums ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Product Terms

5/10/2018 Logic Functions x x x Programmed PLD x x Sums ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Product Terms

5/10/2018 GLUE LOGIC Logic Functions x x x x Programmed PLD x x x Sums ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Product Terms

Complex PLDs CPLDs Programmable PLD Blocks Programmable Interconnects
5/10/2018 CPLDs Programmable PLD Blocks Programmable Interconnects Electrically Erasable links Feedback Outputs CPLD Architecture ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Sequential Circuits 5/10/2018 Combinational Logic (Larger circuits difficult to predict) Synchronous Logic driven by a CLOCK Registers, Flip Flops (Memory) Inputs ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Sequential Circuits 5/10/2018 Combinational Logic (Larger circuits difficult to predict) Synchronous Logic driven by a CLOCK Registers, Flip Flops (Memory) Intermediate New Output every clock edge Inputs Register CLOCK ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time EDGES

Sequential Circuits 5/10/2018 Combinational Logic (Larger circuits difficult to predict) Synchronous Logic driven by a CLOCK Registers, Flip Flops (Memory) Intermediate New Output every clock edge Inputs Clock Rate determines speed Comb Logic Must meet Timing => Predictable circuits Register CLOCK ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Shift Registers, Pipelines, Finite State Machines … EDGES

Field Programmable Gate Arrays FPGA
5/10/2018 Field Programmable Gate Array ‘Simple’ Programmable Logic Blocks Massive Fabric of Programmable Interconnects Standard CMOS Integrated Circuit fabrication process as for memory chips (Moore’s Law) A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible.

5/10/2018 Field Programmable Gate Array ‘Simple’ Programmable Logic Blocks Massive Fabric of Programmable Interconnects Standard CMOS Integrated Circuit fabrication process as for SRAM memory chips (Moore’s Law) Huge Density of Logic Block ‘Islands’ 1,000 … 100,000’s in a ‘Sea’ of Interconnects A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible. FPGA Architecture

5/10/2018 A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible.

Logic Blocks Logic Functions implemented in Look Up Table LUTs.
5/10/2018 Logic Functions implemented in Look Up Table LUTs. Flip-Flops. Registers. Clocked Storage elements. Multiplexers (select 1 of N inputs) ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time FPGA Fabric Logic Block

Look Up Tables LUTs 5/10/2018 LUT contains Memory Cells to implement small logic functions Each cell holds ‘0’ or ‘1’ . Programmed with outputs of Truth Table Inputs select content of one of the cells as output 3 Inputs LUT -> 8 Memory Cells 3 – 6 Inputs ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Static Random Access Memory SRAM cells Multiplexer MUX

Look Up Tables LUTs 5/10/2018 LUT contains Memory Cells to implement small logic functions Each cell holds ‘0’ or ‘1’ . Programmed with outputs of Truth Table Inputs select content of one of the cells as output Configured by re-programmable SRAM memory cells 3 Inputs LUT -> 8 Memory Cells 3 – 6 Inputs ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Static Random Access Memory SRAM cells Multiplexer MUX

Logic Blocks 5/10/2018 Larger Logic Functions built up by connecting many Logic Blocks together ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Logic Blocks 5/10/2018 Larger Logic Functions built up by connecting many Logic Blocks together Determined by SRAM cells SRAM cells ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Clocked Logic Registers on outputs. CLOCKED storage elements.
5/10/2018 Registers on outputs. CLOCKED storage elements. Synchronous FPGA Logic Design, Pipelined Logic. FPGA Fabric Pulse from Global Clock (e.g. LHC BX frequency) ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time FPGA Fabric Special Routing for Clocks Clock from Outside world (eg LHC bunch frequency)

Input Output I/O Getting data in and out
5/10/2018 Input Output I/O Getting data in and out Up to > 1,000 I/O “pins” (several 100 MHz)

Input Output I/O Getting data in and out
5/10/2018 Input Output I/O Getting data in and out Up to > 1,000 I/O “pins” (several 100 MHz) Special I/O SERIALISERS ~ 10 Gbps transfer rates Optical TRx

Designing Logic with FPGAs
5/10/2018 Design Capture. High level Description of Logic Design. Graphical descriptions Hardware Description Language (Textual) ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Hardware Description Languages
5/10/2018 Language describing hardware (Engineers call it FIRMWARE) Doesn’t behave like “normal” programming language ‘C/C++’ Describe Logic as collection of Processes operating in Parallel Language Constructs for Synchronous Logic Compiler (Synthesis) Tools recognise certain code constructs and generates appropriate logic Not all constructs can be implemented in FPGA! 2 Popular languages are VHDL , VERILOG Easy to start learning… Hard to master! ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

VHDL ENTITY Declaration Input Output to Module (STD LOGIC)
5/10/2018 VHDL ENTITY Declaration Input Output to Module (STD LOGIC) SIGNALS Declaration WIRES CONCURRENT ASSIGNMENTS CONDITIONAL ASSIGNMENTS => MULTIPLEXERS

VHDL PROCESS Declaration. CONCURRENT functions. Synchronous Logic.
5/10/2018 VHDL PROCESS Declaration. CONCURRENT functions. Synchronous Logic. COMPONENT Declaration

Designing Logic with FPGAs
5/10/2018 High level Description of Logic Design Hardware Description Language (Textual) Compile (Synthesis) into NETLIST. Boolean Logic Gates. Target FPGA Device Mapping Routing Bit File for FPGA Commercial CAE Tools (Complex & Expensive) Logic Simulation Design Flow ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Configuring an FPGA 5/10/2018 Millions of SRAM cells holding LUTs and Interconnect Routing Volatile Memory. Lose configuration when board power is turned off. Keep Bit Pattern describing the SRAM cells in non-Volatile Memory e.g. PROM or Digital Camera card Configuration takes ~ secs JTAG Port ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Configuring an FPGA 5/10/2018 Millions of SRAM cells holding LUTs and Interconnect Routing Volatile Memory. Lose configuration when board power is turned off. Keep Bit Pattern describing the SRAM cells in non-Volatile Memory e.g. PROM or Digital Camera card Configuration takes ~ secs JTAG Port Programming Bit File ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time JTAG Testing

5/10/2018 Large Complex Functions Re-Programmability, Flexibility. Massively Parallel Architecture Processing many channels simultaneously cf MicroProcessor Fast Turnaround Designs  Standard IC Manufacturing Processes. Moore’s Law  Mass produced. Inexpensive.  Many variants. Sizes. Features.  PP Not Radiation Hard  Power Hungry  No Analogue  A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible.

FPGA Trends State of Art is 40nm on 300 mm wafers
5/10/2018 State of Art is 40nm on 300 mm wafers Top of range >500,000 Logic Blocks >1,000 pins (Fine Pitched BGA) Logic Block cost ~ 1$ in 1990 Today < 0.1 cent Problems Power. Leakage currents. Design Gap CAE Tools ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Summary Programmable Logic Devices FPGA Field Programmable Gate Arrays
5/10/2018 Summary Programmable Logic Devices Basics Evolution FPGA Field Programmable Gate Arrays Architecture Design Flow Hardware Description Languages Design Tools Importance for Particle Physics Experiments

References The Design Warrior’s Guide to FPGAs
5/10/2018 References The Design Warrior’s Guide to FPGAs Clive Maxfield, Newnes Elsevier VHDL for Logic Synthesis Andrew Rushden, Wiley FPGA manufacturer web sites FPGA Online

Spare Slides 5/10/2018 edward.freeman@stfc.ac.uk
library IEEE; call some library's use IEEE.STD_LOGIC_1164.ALL; -- “--” is a comment USE ieee.std_logic_arith.all; -- define a black box for the component needed entity counter is what is the component called port( -- what IO dose it have clk : in std_logic; -- clk = Clock. All synchronous logic has a clock rst : in std_logic; -- rst = reset. Most synchronous logic has a reset. count : out std_logic_vector(7 downto 0) wires in a bundle with no interpretation. ); end counter; -- what logic should be in the black box architecture RTL of counter is -- this version on the content of the black box is called “RTL” begin -- start the logic that is inside the black box process (clk,rst) -- start a process i.e. Sequential logic. The list in brackets is a sensitivity list variable v_count : unsigned ( 7 downto 0); -- declare a local variable called v_count begin -- start logic process if rst = '1' then -- async reset i.e. It dose not wait for a clock edge count <= (others => '0'); -- set all the bits of count to zero v_count := (others => '0'); -- set all bits to zero note variable assignment not signal assignment. elsif clk'event and clk = '1' then -- wait for the rising edge of clock v_count := v_count + 1; -- add one to current value of count and asign to end if; end process; count <= conv_std_logic_vector(v_count,8); end RTL;

Introduction to Programmable Logic Devices

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