1. ELEC 7770 Advanced VLSI Design Spring 2014 Gate Delay and Circuit Timing
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University, Auburn, AL 36849
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

2. Delay of a Transition ic(t) vi (t) vo(t) VDD Ron CL R = large Ground
CL = Total load capacitance for gate; includes transistor capacitances
of driving gate + routing capacitance + transistor capacitances
of driven gates; obtained by layout analysis.
Fall 2015, Nov 30
ELEC Lecture 8 2

3. Charging of a Capacitor
R = Ron
t = 0
i(t)
v(t)
VDD
C = CL
Charge on capacitor, q(t) = C v(t)
Current, i(t) = dq(t)/dt = C dv(t)/dt
Fall 2015, Nov 30
ELEC Lecture 8

4. ∫ ───── = ∫ ──── i(t) = C dv(t)/dt = [VDD – v(t)] /R dv(t) dt
∫ ───── = ∫ ────
VDD – v(t) RC
– t
ln [VDD – v(t)] = ── A RC
Initial condition, t = 0, v(t) = 0 → A = ln VDD
– t
v(t) = VDD [1 – exp(───)] = 0.5VDD RC
t = RC
Fall 2015, Nov 30
ELEC Lecture 8

5. Delay: Definitions Gate delay
Rise time is the time a signal takes to rise from 10% to 90% of its peak value.
Fall time is the time a signal takes to drop from 90% to 10% of its peak value.
Delay of a gate or circuit is the time interval between the input crossing 50% of peak value and the output crossing 50% of peak value.
VDD
GND
90% VDD A
Fall time
10% VDD
Time A B
Gate delay
NOT
gate
1→0
VDD
GND
0→1
90% VDD B
Rise time
10% VDD
Fall 2015, Nov 30
ELEC Lecture 8
Time

6. Inverter: Idealized Input
VDD
GND
INPUT
Gate delay
VDD
0.5VDD
GND
OUTPUT
time
t = 0
0.69CR
Fall 2015, Nov 30
ELEC Lecture 8

7. Timing of a Digital Circuit
Most digital circuits are clocked synchronous finite state machines (FSM). FF FF
Primary
Inputs
Primary
Outputs
Combinational circuit
(Gates interconnected
without feedback) FF FF
Clock FF FF
Fall 2015, Nov 30
ELEC Lecture 8

8. ELEC 7770: Advanced VLSI Design (Agrawal)
Timing Paths
Input
Signal
changes
Output
Observation
instant
Transient
region
Comb.
logic
Inputs
Synchronized
With clock
Outputs
time
Clock period
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

9. Timing Analysis and Optimization
Dynamic analysis: Simulation.
Static timing analysis (STA): Vector-less topological analysis of circuit.
Timing optimization
Performance
Clock design
Other forms of design optimization
Chip area
Testability
Power
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

10. ELEC 7770: Advanced VLSI Design (Agrawal)
Circuit Delays
Switching or inertial delay is the interval between input change and output change of a gate:
Depends on input capacitance, device (transistor) characteristics and output capacitance of gate.
Also depends on input rise or fall times and states of other inputs (second-order effects).
Approximation: fixed rise and fall delays (or min-max delay range, or single fixed delay) for gate output.
Propagation or interconnect delay is the time a transition takes to travel between gates:
Depends on transmission line effects (distributed R, L, C parameters, length and loading) of routing paths.
Approximation: modeled as lumped delays for gate inputs.
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

11. ELEC 7770: Advanced VLSI Design (Agrawal)
Spice
Circuit/device level analysis
Circuit modeled as network of transistors, capacitors, resistors and voltage/current sources.
Node current equations using Kirchhoff’s current law.
Analysis is accurate but expensive
Used to characterize parts of a larger circuit.
Original references:
L. W. Nagel and D. O. Pederson, “SPICE – Simulation Program With Integrated Circuit Emphasis,” Memo ERL-M382, EECS Dept., University of California, Berkeley, Apr
L. W. Nagel, SPICE 2, A Computer program to Simulate Semiconductor Circuits, PhD Dissertation, University of California, Berkeley, May 1975.
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

12. Logic Model of MOS Circuit
VDD
pMOS FETs a Da Dc c a Ca b Db c Cc b
Da and Db are
interconnect or
propagation delays
Dc is inertial delay
of gate Cb
nMOS
FETs Cd
Ca , Cb , Cc and Cd are
node capacitances
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

13. Spice Characterization
Input data pattern
Delay (ps)
Dynamic energy (pJ)
a = b = 0 → 1 69
1.55
a = 1, b = 0 → 1 62
1.67
a = 0 → 1, b = 1 50
1.72
a = b = 1 → 0 35
1.82
a = 1, b = 1 → 0 76
1.39
a = 1 → 0, b = 1 57
1.94
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

14. Spice Characterization (Cont.)
Input data pattern
Static power (pW)
a = b = 0
5.05
a = 0, b = 1
13.1
a = 1, b = 0
5.10
a = b = 1
28.5
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

15. Complex Gates: Switch-Level Partitions
Circuit partitioned into channel-connected components for Spice characterization.
Reference: R. E. Bryant, “A Switch-Level Model and Simulator for MOS Digital Systems,” IEEE Trans. Computers, vol. C-33, no. 2, pp , Feb
Internal switching nodes not seen by logic simulator G2 G1 G3
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

16. Interconnect Delay: Elmore Delay Model
W. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol. 19, no.1, pp , Jan 2 R2 C2 R1 1 s 4 R4 C1 C4 R3 3
Shared resistance:
R45 = R1 + R3
R15 = R1
R34 = R1 + R3 R5 C3 5 C5
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

17. ELEC 7770: Advanced VLSI Design (Agrawal)
Elmore Delay Formula N
Delay at node k = 0.69 Σ Cj × Rjk
j=1
where N = number of capacitive nodes in the network
Example:
Delay at node 5 = 0.69 [ R1 C1 + R1 C2 + (R1+R3)C3 + (R1+R3)C4
(R1+R3+R5)C5 ]
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

18. Event Propagation Delays
Single lumped inertial delay modeled for each gate
PI transitions assumed to occur without time skew
Path P1
1 3 1 P2 1 2 3 P3 5 2
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

19. ELEC 7770: Advanced VLSI Design (Agrawal)
Circuit Outputs
Each path can potentially produce one signal transition at the output.
The location of an output transition in time is determined by the delay of the path.
Clock period
Final value
Initial value
Fast transitions
Slow transitions
time
Initial value
Final value
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

20. Delay and Discrete-Event Simulation (NAND gate)
Transient
region a
Inputs b
c (CMOS)
c (zero delay)
c (unit delay)
Logic simulation X
c (multiple delay)
rise=5, fall=5
Unknown (X)
c (minmax delay)
min =2, max =5 5
Time units
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

21. Event-Driven Simulation (Example)
Scheduled
events
c = 0
d = 1, e = 0
g = 0
f = 1
g = 1
Activity
list
d, e
f, g g
a =1
e =1
t = 0 1 2 3 4 5 6 7 8 2
c =1→0
g =1 2 2
d = 0
Time stack 4
f =0
b =1 g 4 8
Time, t
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

22. Time Wheel (Circular Stack)
max
Current
time
pointer
t=0
Event link-list 1 2 3 4 5 6 7
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

23. Timing Design and Delay Test
Timing simulation:
Critical paths are identified by static (vector-less) timing analysis tools like Primetime (Synopsys).
Timing or circuit-level simulation using designer-generated functional vectors verifies the design.
Layout optimization: Critical path data are used in placement and routing. Delay parameter extraction, timing simulation and layout are repeated for iterative improvement.
Testing: Some form of at-speed test is necessary. Critical paths and all gate transition delays are tested.
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

24. Static Timing Analysis (STA)
Finds maximum and minimum delays between all clocked flip-flops.
Flip-flops
Combinational
circuit
Flip-flops
Flip-flops
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

25. ELEC 7770: Advanced VLSI Design (Agrawal)
Early References
T. I. Kirkpatrick and N. R. Clark, “PERT as an Aid to Logic Design,” IBM J. Res. Dev., vol. 10, no. 2, pp , March 1966.
R. B. Hitchcock, Sr., “Timing Verification and the Timing Analysis Program,” Proc. 19th Design Automation Conf., 1982, pp
V. D. Agrawal, “Synchronous Path Analysis in MOS Circuit Simulator,” Proc. 19th Design Automation Conf., 1982, pp
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

26. ELEC 7770: Advanced VLSI Design (Agrawal)
Basic Ideas
Adopted from project management
Frederick W. Taylor ( )
Henry Gantt ( )
PERT – Program Evaluation and Review Technique
CPM – Critical Path Method
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

27. A Gantt Chart in Microsoft Excel
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

28. ELEC 7770: Advanced VLSI Design (Agrawal)
Using a Gantt Chart
Track progress of subtasks and project.
Assess resource needs as a function of time.
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

29. PERT (Program Evaluation and Review Technique) Chart
Milestones Activities
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

30. Example: Thesis Research
Begin
Defense
done
Analysis
completed
2, 3, 4
2, 2, 2
2, 4, 6 weeks
4, 4, 4
4, 5, 6
Thesis
Draft
done
Problem
selected
Background
study
completed
1, 2, 3
Thesis
submitted
3, 4, 5
5, 7, 9
4, 4, 4
1,2,3
minimum
average
maximum
2, 4, 6
Draft
revisions
Program
and
Experiment
completed
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

31. ELEC 7770: Advanced VLSI Design (Agrawal)
Critical Path
Critical path is path of maximum average delay (26 weeks).
Begin
Defense
done
Analysis
completed
2, 3, 4
2, 2, 2
2, 4, 6 weeks
4, 4, 4
4, 5, 6
Thesis
Draft
done
Problem
selected
Background
study
completed
1, 2, 3
Thesis
submitted
3, 4, 5
5, 7, 9
4, 4, 4
1,2,3
minimum
average
maximum
2, 4, 6
Draft
revisions
Program
and
Experiment
completed
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

32. Timing Analysis Using PERT
H. Chang and S. S. Sapatnekar, “Statistical Timing Analysis
Considering Spatial Correlations Using a Single PERT_Like
Traversal,” Proc. International Conf. on Computer-Aided
Design, 2003, pp
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

33. Large Circuit Timing Analysis
Determine gate delays:
From layout analysis, or use approximate delays:
Gate delay increases in proportion to number of fanouts (increased capacitance)
Delay decreases in proportion to increase in gate size (reduced transistor channel resistance)
Purpose of analysis is to verify timing behavior – determine maximum speed of operation.
Methods of analysis:
Circuit simulation – most accurate, expensive (Spice program)
Static timing analysis (STA) – most efficient, approximate
Fall 2015, Nov 30
ELEC Lecture 8

34. Static Timing Analysis (STA)
Combinational logic for critical path delays.
Circuit represented as an acyclic directed graph (DAG).
Gates characterized by delays; gate function ignored.
No inputs are used – worst-case analysis – static analysis (simulation would be dynamic).
Fall 2015, Nov 30
ELEC Lecture 8

35. Combinational Circuit of an FSM1 H 1 H 1
Gate delay B 1 E 4 G 1
Fanout = 4 C 2 J 1 F 2 D 1
Input to Output delay must not exceed clock period
Fall 2015, Nov 30
ELEC Lecture 8

36. Static Timing Analysis (STA) Step 1
Levelize circuit. Initialize arrival times at primary inputs to 0. A 1 H 1 B 1 E 4 G 1 C 2 J 1 F 2 D 1
Level of a gate is one greater than
the maximum of fanin gate levels
Level
Fall 2015, Nov 30
ELEC Lecture 8

37. Static Timing Analysis (STA) Step 2
Determine output arrival times of gates in level order. 1 A 1 10 H 1 B 1 1 6 E 4 G 1 9 C 2 2 J 1 9 F 2 8 D 1 1
Arrival time at a gate output
= maximum of input arrivals + gate delay
Level
Fall 2015, Nov 30
ELEC Lecture 8

38. Static Timing Analysis (STA) Step 3
Trace critical paths from the output with longest arrival time. 1 A 1 10 H 1 B 1 1 6 E 4 9 G 1 C 2 2 J 1 9 F 2 8 D 1 1
Critical path: C, E, F, G, H; delay = 10
Level
Fall 2015, Nov 30
ELEC Lecture 8

39. Characteristics of STA
Linear time analysis, Complexity is O(n), n is number of gates and interconnects.
Variations:
Find k longest paths:
S. Kundu, “An Incremental Algorithm for Identification of Longest (Shortest) Paths,” Integration, the VLSI Journal, vol. 17,  no. 1, pp , August 1994.
Find worst-case delays from an input to all outputs.
Linear programming methods.
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

40. Algorithms for Directed Acyclic Graphs (DAG)
Graph size: n = |V| + |E|, for |V| vertices and |E| edges.
Levelization: O(n) (linear-time) algorithm finds the maximum (or minimum) depth.
Path counting: O(n2) algorithm. Number of paths can be exponential in n.
Finding all paths: Exponential-time algorithm.
Shortest (or longest) path between two nodes:
Dijkstra’s algorithm: O(n2)
Bellman-Ford algorithm: O(n3)
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)

41. ELEC 7770: Advanced VLSI Design (Agrawal)
References
Delay modeling, simulation and testing:
M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000.
Analysis and Design:
G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.
N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, 1999.
PrimeTime (Static timing analysis tool):
H. Bhatnagar, Advanced ASIC Chip Synthesis, Second Edition, Springer, 2002
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)