1. ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN
Dr. Shi
Dept. of Electrical and Computer Engineering

2. STATE REDUCTION

3. Overview Important to minimize the size of digital circuitry
Analysis of state machines leads to a state table (or diagram)
In many cases reducing the number of states reduces the number of gates and flops
This is not true 100% of the time
In this course we attempt state reduction by examining the state table
Other, more advanced approaches, possible
Reducing the number of states generally reduces complexity.

4. FSM Optimization State Reduction: Example: Odd parity checker
Motivation:
lower cost
fewer flip-flops in one-hot implementations
possibly fewer flip-flops in encoded implementations
more don’t cares in next state logic
fewer gates in next state logic
Simpler to design with extra states then reduce later.
Example: Odd parity checker

5. State Reduction “Row Matching” is based on the state-transition table:
If two states
have the same output and
both transition to the same next state and self-loop
or both transition to each other
then they are equivalent.
Combine the equivalent states into a new renamed state.
Repeat until no more states are combined
NS output
PS x=0 x=1
S0 S0 S
S1 S1 S
S2 S2 S
State Transition Table

6. FSM Optimization Merge state S2 into S0 Eliminate S2
New state machine shows same I/O behavior
Example: Odd parity checker.
NS output
PS x=0 x=1
S0 S0 S
S1 S1 S
State Transition Table

7. Row Matching Example State Transition Table NS output
PS x=0 x=1 x=0 x=1
a a b
b c d
c a d
d e f
e a f
f g f
g a f
State Transition Table

8. Row Matching Example NS output PS x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0
c a d
d e f
e a f
f e f
Reduced State Transition Diagram
NS output
PS x=0 x=1 x=0 x=1
a a b
b c d
c a d
d e d
e a d

9. Partitioning Minimization (Moore)
Step 1: P1= (abcdefg)
Step 2: P2=(abd)(cefg)
Step 3:
(abd) 0-successors (bdb)
(abd) 1-successors (cfg)
(cefg) 0-successors (ffef)
(cefg) 1-successors (ecdg)
P3: (abd)(ceg)(f)
NS output
PS x=0 x=1
a b c
b d f
c f e
d b g
e f c
f e d
g f g
State Transition Table

10. Partitioning Minimization
Step 3: P3: (abd)(ceg)(f)
Step 4:
(abd) 0-successors (bdb)
(abd) 1-successors (cfg)
 b must be removed
(ceg) 0-successors (fff)
(ceg) 1-successors (ecg)
P4: (ad)(b)(ceg)(f)
NS output
PS x=0 x=1
a b c
b d f
c f e
d b g
e f c
f e d
g f g
State Transition Table

11. Partitioning Minimization
Step 4: P4: (ad)(b)(ceg)(f)
Step 5: (verify no change)
NS output
PS x=0 x=1
a b c
b a f
c f c
f c a
State Transition Table

12. STATE ASSIGNMENT

13. Encoding State Variables
Option 1: Binary values
000, 001, 010, 011, 100 …
Option 2: Gray code
000, 001, 011, 010, 110 …
Option 3: One hot encoding
One bit for every state
Only one bit is a one at a given time
For a 5-state machine
00001, 00010, 00100, 01000, 10000

14. Summary Important to create smallest possible FSMs
This course: use visual inspection method
Often possible to reduce logic and flip flops
State encoding is important
One-hot coding is popular for flip flop intensive designs.
credential:
bring a computer
die photo
wafer :
This can be an hidden slide. I just want to use this to do my own planning.
I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may
We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.
Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.