1. Fri. Aug 25 Announcements HW 1 / Lab 1 next week Slides online
Tools and fundamentals of instructions
Remember no in-lab quiz but HWs still marked
Slides online
Complete class for last year
This year’s slides available as I mod/create them.
First In-Class Quiz Monday
First 10 minutes of class
Make sure clickers are registered
You can have any resources you want/need

2. Module 1-B
ISA Overview
Tim Rogers 2017

3. Learning Outcome #1 Architecture and Programming Model
“An ability to program a microcontroller to perform various tasks”
Architecture and Programming Model
Instruction Set Overview
Assembly Control Structures
Control Structure Applications
Table Lookup
Parameter Passing
Macros and Structured Programming
How?

4. Objective Why? 362 Student’s Perspective? Prof. Meyer’s Perspective
“Instruction Set Overview”
Why?
362 Student’s Perspective?
Prof. Meyer’s Perspective
Prof. Rogers’ Perspective
Actual ECE 362 Meme (Author unknown)

5. Notation for numbers Notation How Used Examples Prefix: $ Suffix: h/H
hexadecimal (base 16) number
$1234 = 1234h = 1234H =
Prefix:!
Suffix: t/T
decimal (base 10) number
!1234 = 1234t = 1234T =
Prefix: % Suffix: b/B
binary (base 2) number
% = b = B =

6. Review of conversions Easy to convert between power-2 bases
Formally can always break/group pow-2 bases
num_bits = log2(base)

7. Short Cut for Conversion Among Powers of 2
Exercise: Convert (110101)2 to base 16 (hex)
Exercise: Convert (A3F)16 to base 2 (binary)

8. ”In your head” power two conversions
25 = 32
Many way to think about this
My approach: Remember way-points
210 = 1024 =1k
220 = 1024k = 1M
So when I asked you how much memory in 16-bits (216):
Take the exponent, break into “easy” waypoints: 16
= 10
+ 5
+ 1 1k
x 32
x 2
= 64k

9. General Notation Notation How Used Examples ( )
( )
contents of register/memory location
(A)
(0800h) ;
beginning of a comment
LDAA 0800h ; (A) = (0800h) :
concatenation of two quantities
16-bit result in (A):(B)  (D)
32-bit result in (D):(X)

10. General Notation Notation How Used Examples  
assignment or “copy” (arrow points to destination)
(A)  (B) means load the A register with the contents of the B register (the contents of B remains the same) 
exchange (or “swap”) of contents
(D)  (X) means exchange the contents of the D and X registers ~
shorthand for number of instruction execution cycles
assuming an 8 MHz bus clock, each cycle is 125 ns (nanoseconds) 
(bit-wise) complement
mask means the bit-wise complement of mask

11. Addressing Notation Notation How Used Examples addr
effective address for operand
LDAA addr ; (A) = (addr) #
immediate addressing when used before const. operand
LDAA #80h ; (A) = 80h
LDAA #$12 ; (A) = 12h
LDAA #$A5 ; (A) = A5h
LDAA # b ; (A) = AAh ,
indexed addressing when placed between two entities in the operand field
LDAA 2,X ; (A) = ((X) + 2)
STAA D,Y ; ((D)+(Y)) = (A)
[ ]
indirect addressing when used to bracket the operand field
STAA [2,X] ; (((X)+2):((X)+3)) = (A)
LDAA [D,Y] ; (A) = (((D)+(Y)):((D)+(Y)+1))

12. Addressing Mode and Operands
Typically in our accumulator ISA:
One operand is a register that is also the output
Other comes from memory
Operand
Operand
Output
Some exceptions:
Store outputs to memory
Only one operand in some instructions
Memory
Addressing mode determines where instruction inputs/outputs come from / go to

13. Operands implicit from opcode
Inherent Addressing
Abbrev.
Name
Description
Examples
INH
Inherent
Operand[s] in register[s]
DAA
DEX
Example Instruction X
Assembly
Instruction
opcode
DEX
Operands implicit from opcode -1

14. Value of operand encoded in instruction.
Immediate Addressing
Abbrev.
Name
Description
Examples
IMM
Immediate
Operand follows #.
Value embedded in instruction.
LDAA #$FF
ADDA #3
Example Instruction
Value of operand encoded in instruction. A
Assembly
Instruction
opcode
immediate
ADDA #3

15. Eff. Address of operand encoded in instruction.
Direct Addressing
Abbrev.
Name
Description
Examples
DIR/EXT
Direct/Extended
Effective memory address in instruction.
Direct = 1B addr. Extended = 2B addr.
LDAA $FF ; direct
ADDA $88FF ; extended A
Example Instruction
Eff. Address of operand encoded in instruction.
Memory
Assembly
Instruction
opcode
addr high
addr low
ADDA $88FF
Eff. Address

16. Mon Aug. 28 Announcements
To refresh anything on the course website use shift+refresh…
Error in the slides?
Good catch! Post it to piazza, I will correct it and you will get bonus credit.

17. Addressing Mode Types Inherent Immediate Direct/Extended
Indexed with constant
Indexed with accumulator offset
Indexed with auto pre/post inc/dec
Indexed-Indirect with constant offset
Indexed-Indirect with Accumulator Offset

18. Indexed with constant offset
Abbrev.
Name
Description
Examples
IDX
IDX1
IDX2
Indexed with Constant Offset
Eff. address = (<X|Y|SP|PC>) + signed_const
IDX=5-bit const
IDX1=9-bit const
IDX2=16-bit const
LDAA 0,X
STAA -50,Y
ADDA 1024,X X A
Example Instruction
Post-byte which index register
Const. offset encoded in instruction.
Memory
Assembly
Instruction
opcode
post-byte
offset high
offset low
ADDA 1024,X
Eff. Address +

19. Indexed with accumulator offset
Abbrev.
Name
Description
Examples
IDX
Indexed with Accumulator Offset
Eff. address = (<X|Y|SP|PC>) + (A|B|D)
Accumulator is treated as unsigned
LDAA B,X
STAA A,X
ADDA A,X X A
Example Instruction +
Post-byte defines which index register + accumulator.
Memory
Eff. Address
Assembly
Instruction
opcode
post-byte
ADDA A,X

20. Indexed with auto increment/decrement
Abbrev.
Name
Description
Examples
IDX
Indexed with Auto Pre-/Post- Increment or Decrement
Eff. address = (<X|Y|SP|PC>) + signed_const
Can inc/dec index reg. before/after use.
Const range: 1-8
LDAA 1,-Y ; pre-dec
STAA 2,+SP ; pre-inc
ADDA 8,PC- ; post-dec
ADDA 8,X+ ; post-inc X A
Example Instruction +
Inc/dec value encoded in instruction
Eff. Address
Memory
Post-byte defines which index register.
Assembly
Instruction
opcode
post-byte
ADDA 8,X+

21. Indexed-Indirect with constant offset
Abbrev.
Name
Description
Examples
[IDX2]
Indexed-Indirect with Constant Offset
Eff. address = ((<X|Y|SP|PC>) + signed_const)
LDAA [0,Y]
ADDA [5,X] X A
Example Instruction
Memory
Assembly
Instruction
opcode
post-byte
offset high
offset low
ADDA [5,X]
2 memory lookups
Indirect
Address +
Eff Address (H)
Eff Address (L)

22. Indexed-Indirect with accumulator offset
Abbrev.
Name
Description
Examples
[D,IDX]
Indexed-Indirect with Accumulator Offset
Eff. address = ((<X|Y|SP|PC>) + (D))
LDAA [D,Y]
ADDD [D,X] X D
Example Instruction +
Indirect
Address
Memory
Assembly
Instruction
opcode
post-byte
ADDD [D,X]
2 memory lookups
Eff Address (H)
Eff Address (L)

23. ‘Pointless’ Clicker question #1
Do you ‘think’ you understand indirect addressing:
A: Yes
B: No
Do you ‘think’ you understand indirect addressing:
A: Yes 
B: No

24. ‘Pointless’ Clicker Question #2
Memory
Addr
Value
What is the result after the instruction:
ADDA 2,X
A: A=12t, X = 0t
B: A=17t, X = 0t
C: A=21t, X = 2t
D: A=21t, X = 0t
E: I am too lost to try…
What is the result after the instruction:
ADDA 2,X
A: A=12t, X = 0t
B: A=17t, X = 0t 
C: A=21t, X = 2t
D: A=21t, X = 0t
E: I am too lost to try… 0t 1 2t 2 7t 3 0t
Regs
Name
Value A
10t X 0t
65534 7t

25. ‘Pointless’ Clicker Question #3
Memory
Addr
Value
What is the result after the instruction:
ADDA [0,X]
A: A=12t, X = 0t
B: A=17t, X = 0t 
C: A=21t, X = 2t
D: A=21t, X = 0t
E: I am too lost to try…
What is the result after the instruction:
ADDA [0,X]
A: A=12t, X = 0t
B: A=17t, X = 0t
C: A=21t, X = 2t
D: A=21t, X = 0t
E: I am too lost to try… 0t 1 2t 2 7t 3 0t
Regs
Name
Value A
10t X 0t
65534 7t

26. Instruction classes Data Transfer Arithmetic Logical
Transfer of control (branch/jump)
Machine control
“special” or “weird”
Every instructions in ISA listed in 2 places:
Quick reference:
Detailed Description:

27. Data Transfer Instructions
Register to Register:
Transfer (Move)
Swap Regs:
Exchange
Just move data B 4 3 A 2
Register to Memory:
Store/Stack Push 1
Memory to Register:
Load/Stack Pop 5
Copy Memory:
Move
Memory

28. Wed Aug. 30 Announcements Quiz results uploaded to blackboard
Ended up being out of 8 (5 in actual quiz + 3 ‘pointless’ questions).
Everyone just got a point for the ’pointless’ questions.

29. Loads/Stores Move data between registers and memory
Note: These instructions will change condition register (CCR) bits.
1-6 cycles dep. on addressing mode
Move data between registers and memory
Can use different addressing modes
Description
Assembly mnemonic
operation
Examples
Load register with memory value
LDA<A|B> addr; 8-bit
LD<D|X|Y|S> addr; 16-bit
(<A|B|C|D|X|Y|SP|PC>)  (addr)
LDAA #4
LDAB [D,X]
Store register into memory
STA<A|B> addr; 8-bit
ST<D|X|Y|S> addr; 16-bit
(<A|B|C|D|X|Y|SP|PC>)  (addr)
STAA $4
STD [0,Y]
Which addressing modes make no sense in stores?

30. Exchange Some complications, can you guess when?B
Exchange A
Note: Only “Inherent” addressing used
Swap register contents
Description
Assembly mnemonic
operation
Examples
Exchange
Register Contents
EXG <ANY>,<ANY>
(<ANY>)  (<ANY>)
EXG A,B
EXG A,X
Some complications, can you guess when?
8-bit
16-bit
Does not change CCR bits.
All take 1 cycle.
Lower ½
16-bit
8-bit

31. Transfer (Copy) RegisterB
Transfer (Copy) Register A
Copy one register to another
Note: Only “Inherent” addressing used
Description
Assembly mnemonic
operation
Examples
Copy Register
TFR <ANY>,<ANY>
(<ANY>)  (<ANY>)
TFR A,B
TFR A,X
Some complications, can you guess when?
8-bit
16-bit
Sign-extension
8-bit
Does not change CCR bits.
All take 1 cycle.
16-bit
8-bit
Lower ½
16-bit

32. Does not change CCR bits.
Move (Copy) Memory
Copy memory values
Description
Assembly mnemonic
operation
Examples
Copy 1B Memory
MOVB addr1,addr2 ; 8-bits
(addr1)  (addr2)
MOVB #1, $900
MOVB 1,X+,2,Y+
Copy 2B Memory
MOVW addr1,addr2 ; 16-bits
(addr1+1)  (addr2+1)
MOVW #1, 0, X
MOVW 1,X+,2,Y+
addr1: IMM, DIR, INDEXED
Addr2: DIR, INDEXED
Does not change CCR bits.
4-6 cycles.

33. Stack grows down (in addresses)
Memory
Stack Review
Addr
Value …
First In Last Out (FILO) or Last In First Out (LIFO) Data Structure 1 …
Stack grows down (in addresses) 99
10t
Regs
PULA SP
100 …
Name
Value
PSHB A 5t B
10t
10t SP …
99t
100t
65535

34. Stack Instructions Save and retrieve data from stack
Note: PULC overwrite CC register
PSH: 2 cycles
PUL: 3 cycles
Save and retrieve data from stack
Description
Assembly mnemonic
operation
Examples
Push Register to Stack
PSH<A|B|C> ; 8-bits
(SP)  (SP) - 1
((SP))  <A|B|C>
PSHA ‘’
PSH<D|X|Y>; 16-bits
((SP))  (lower-8-bits<D|X|Y>)
((SP))  (upper-8-bits<D|X|Y>)
PSHY
Pull (Pop) Register from Stack
PUL<A|B|C>; 8-bit
(<A|B|C>)  ((SP))
(SP)  (SP) + 1
PULB
PUL<D|X|Y>; 16-bit
(upper-8-bits<D|X|Y>)  ((SP))
(lower-8-bits<D|X|Y>)  ((SP))
PULX

35. Instruction Classes Data Transfer Arithmetic Group Logical
Transfer of control (branch/jump)
Machine Control
“Special”

36. Arithmetic Instructions
Heart of the ISA.
Performs arithmetic
Add
Subtract
Multiply
Divide
Compare/Test
Complement
Increment/Decrement
Min/Max

37. Add
Note: CC bits were made for these instructions. N/Z/V/C/H are all effected
1-6 cycles, depending on addressing mode
Description
Assembly mnemonic
operation
Examples
Add contents of memory to register
ADD<A|B> addr; 8-bit
(<A|B>)  (<A|B>) + (addr)
ADDA #4
ADDB [2,X] ’’
ADC<A|B> addr; 8-bits
(<A|B>)  (<A|B>) + (addr) + (c)
ADCA #4
ADCB [2,X]
ADDD addr; 16-bit
(D)  (D) + (addr):(addr+1)
ADDD $900
ADDD 1,X

38. Subtract What is missing from ADD/SUB?
Note: CC bits were made for these instructions. N/Z/V/C/H are all effected
Description
Assembly mnemonic
operation
Examples
Subtract contents of memory to register
SUB<A|B> addr; 8-bit
(<A|B>)  (<A|B>) - (addr)
SUBA #4
SUBB [2,X] ’’
SBC<A|B> addr; 8-bits
(<A|B>)  (<A|B>) - (addr) - (c)
SUBD addr; 16-bit
(D)  (D) - (addr):(addr+1)
SUBD $900
SUBD 1,X
Modes/structure identical to addition
What is missing from ADD/SUB?

39. Load Effective Address (LEA)
Can think of it as a way to perform arithmetic on 16-bit registers
Simply:
(X)  (X) + 2
Description
Assembly mnemonic
operation
Examples
Compute address, store it in register
LEA<X|Y|S> addr
(<X|Y|S>)  addr
LEAX 2, X
LEAY B, X
LEAY 2, -X
Can use any Indexed addressing mode

40. Register-to-Register Add
Description
Assembly mnemonic
operation
Examples
Add Registers
ABA
(A)  (A) + (B) ‘’
AB<X|Y>
(<X|Y>)  $00:(B) + (<X|Y>)
ABX
ABY
Are replaced with:
LEAX B,X
LEAY B,Y

41. Overflow Dependent on the integer bit-width
Occurs because the result is larger (or smaller) than can be represented in the fixed bit-width
Ex: 8-bit numbers
255t+1t=256t
$FF + $1 = $100 = $00 (in 8-bits)
Generally you can detect overflow if:
Adding 2 +ive numbers results in the –ive number
Adding 2 –ive numbers results in a +ive number
Adding numbers of opposite signs CANNOT result in overflow
Note: You can also detect overflow if the carry-in to the sign-bit is different from the carry-out bit

42. Other conditions (all bits in CCR register)
Zero: Result was zero
Negative: Highest bit is ‘1’
Carry/Borrow: Carry-out of the sign position after addition or borrow out of the sign position after subtraction.

43. Review: Packed Binary Coded Decimal
4-bits to describe a digit between 0-9
$A-$F not used
2 digits in every byte.
Want to perform “normal” binary addition on data in BCD format
Problem: Normal addition does not know about BCD
Solution: Add special “adjusting” instruction

44. MUST be run after ADD|ADC|ABA
Decimal Adjust
Note: Just an adjustment.
MUST be run after ADD|ADC|ABA
Description
Assembly mnemonic
operation
Examples
Decimal Adjust A
DAA
Decimal adjust the result of ADD, ADC, or ABA

45. ADD of BCD Operands Followed by DAA
DAA

46. ADD of BCD Operands Followed by DAA
115
DAA

47. ADD of BCD Operands Followed by DAA
DAA
result of ADD

48. ADD of BCD Operands Followed by DAA
+0110
DAA
result of ADD
since L.N. > 9,
add 6 to adjust

49. ADD of BCD Operands Followed by DAA
+0110
DAA
result of ADD
since L.N. > 9,
add 6 to adjust

50. ADD of BCD Operands Followed by DAA
+0110
DAA
result of ADD
since L.N. > 9,
add 6 to adjust
since U.N. > 9,
add 6 to adjust

51. ADD of BCD Operands Followed by DAA
+0110
DAA
result of ADD
since L.N. > 9,
add 6 to adjust
since U.N. > 9,
add 6 to adjust
CF is hundred’s position

52. ADD of BCD Operands Followed by DAA
+0110
DAA
result of ADD
since L.N. > 9,
add 6 to adjust
since U.N. > 9,
add 6 to adjust
CF is hundred’s position
ten’s one’s

53. Multiply Description Assembly mnemonic operation Examples
8x8 unsigned integer multiply
MUL
(D)  (A) x (B)
16x16 unsigned integer multiply
EMUL
(Y):(D)  (D) x (Y)
16x16 signed integer multiply
EMULS
Note: “special” addressing mode
Description
Assembly mnemonic
operation
Examples
16x16 integer multiply and accumulate
EMACS addr
(addr):(addr+1):(addr+2):(addr+3) 
(addr):(addr+1):(addr+2):(addr+3) +
( ((X)) x ((Y)) )
EMACS

54. Divide Description Assembly mnemonic operation Examples
1616 unsigned integer divide
IDIV
(X)  (D)  (X)
(D)  remainder
1616 signed integer divide
IDIVS
3216 unsigned integer divide
EDIV
(Y)  (Y):(D)  (X)
3216 signed integer divide
EDIVS
1616 unsigned fraction divide
FDIV
Assumes operands are unsigned binary fractions

55. Unsigned Binary Fractions
Do we need an FMUL?
A: Yes
B: No
Do we need an FMUL?
A: Yes
B: No 
Motivation:
Number <1
MSB of unsigned binary fraction is 2-1
What is the result of FDIV produced when dividing $2000 by $8000?
A: $0000
B: $4000
C: $8000
D: $FFFF
E: none of the above
What is the result of FDIV produced when dividing $2000 by $8000?
A: $0000
B: $4000 
C: $8000
D: $FFFF
E: none of the above

56. Fri Sept. 1 Announcements
No Class/Lab Office Hours Monday
In class Quiz on Wednesday Sept 6th
Even if there is no formal quiz – bring your clicker for participation questions
HW 2/ Lab 2 are available and have been all week (I forgot to update the dates)
Slides updated based on bugs found
In particular some clarification around indirect addressing

57. Compare operations Important for conditional branch operations
; Usual branch operation
CMPA #$FF ;First compare A to $FF
BGT label ;If A is > $FF, branch to label

58. Compare/Test
You can compare 2 numbers (<,>,=,>=,<=) by subtracting them and looking at the CCR register
Description
Assembly mnemonic
operation
Examples
Compare Accumulators
CBA
Set CCR based on (A) – (B)
Compare Register with Memory
CMP<A|B> addr
Set CCR based on (<A|B>) - (addr)
CMPA #2
CMPB 2,X ‘’
CP<X|Y|S|D> addr
Set CCR based on
(<X|Y|S|D>) - (addr):(addr+1)
CPD $50
Test for Register for Zero
TST<A|B>
Set CCR based on (<A|B>) - $00
TSTA
TSTB
Test for Memory for Zero
TST addr
Set CCR based on (addr) - $00
TST 1,X
TST $900
Sets CCR based on subtraction without actually storing the subtracted result

59. Other Arithmetic Instruction Types
Add
Subtract
Multiply
Divide
Compare/Test
Complement
Increment/Decrement
Min/Max
Fairly Obvious.
See Manual for Details

60. Instruction Classes Data Transfer Arithmetic Group Logical
Transfer of control (branch/jump)
Machine Control
“Special”

61. Logical Instructions Boolean Shift, rotate Set/Clear
If Arithmetic is the heart, logical/control instructions are the brain
Boolean
Shift, rotate
Set/Clear

62. Boolean Operations AND/OR/EOR
Which instruction would you use to clear bits of the CCR?
A: ORCC
B: ANDCC 
Which instruction would you use to clear bits of the CCR?
A: ORCC
B: ANDCC
AND/OR/EOR
Operate on <A|B> with various addressing modes
Detailed in manual
Useful to set and clear bits of CCR
Description
Assembly mnemonic
operation
Examples
ANDCC
ANDCC immediate
(CCR)  (CCR) bitwise-AND immediate
ANDCC #$FE
ORCC
ORCC immediate
(CCR)  (CCR) bitwise-OR immediate
ORCC #$01
There are also instructions to set/clear individual of the CCR
example: CLC ; clears carry-bit
Only immediate

63. Rotate vs Arithmetic Shift vs Logical Shift
Type
Operation
Assembly
Rotate left
ROL <addr|A|B>
Rotate right
ROR <addr|A|B>
Arithmetic shift left
ASL <addr|A|B|D>
Arithmetic shift right
ASR <addr|A|B>
Logical shift left
LSL <addr|A|B|D>
Logical shift right
LSR <addr|A|B|D>
Actually same operation

64. Clearing, Setting and Testing bit in Memory
Mask is always a constant
Description
Assembly mnemonic
operation
Examples
Bit Clear
BCLR addr, mask
(addr)  (addr) bitwise-AND mask’
BCLR $50, 01
Bit Set
BSET addr, mask
(addr)  (addr) bitwise-OR (mask)
BSET 1, X, $FE
Description
Assembly mnemonic
operation
Examples
Bit Test
BIT<A|B> addr
Set CCR based on:
(<A|B>) bitwise-AND (addr)
BITA #1
BITB 900h
These instructions very useful for controlling peripherals
Useful to test if bits in memory are set

65. Instruction Classes Data Transfer Arithmetic Group Logical
Transfer of control (branch/jump)
Machine Control
“Special”

66. Transfer of Control Instructions
If Arithmetic is the heart, logical/control instructions are the brain
for (int i = 0; i < n; ++i) {
// do stuff }
if (/**/) {
} else {
// do other stuff
int result = foo(a);
Unconditional jumps/branches
Subroutine linkage (function calling)
Conditional branches
Compound test and branch

67. Unconditional Jumps and Branches
Description
Assembly mnemonic
operation
Examples
Jump to PC
JMP addr
(PC)  addr
JMP $900
JMP 0,X
JMP [0,Y]
Branch to PC
BRA rel8
(PC)  (PC) + rel8
BRA label
Long Branch to PC
LBRA rel16
(PC)  (PC) + rel16
LBRA label
Jumps absolute.
Branches relative.
Use label, assembler figures out offset

68. How the branch offset is computed
Encoded offset is dependent on the instruction length
Remember: PC points to next instruction
org h 2
0800 [01] 20FE short bra short 4
0802 [04] 1820FFFC long lbra long 6
end 8 9
Symbol Table
LONG
SHORT -2
2-byte instruction
4-byte instruction -4

69. Calling a function (aka subroutine)
Move PC to function
void foo() {
// do stuff }
int main() {
// do stuff
foo(); }
Move PC Back

70. Subroutine Linkage (Function Calling)
Description
Assembly mnemonic
operation
Examples
Jump to subroutine
JSR addr
(SP)  (SP) – 2
((SP))  (PCh)
((SP)+1)  (PCl)
(PC)  addr
JSR $900
JSR 0,X
JSR [D,Y]
Branch to subroutine
BSR rel8
(PC)  (PC) + rel8
BSR label
Return from subroutine
RTS
(PCh)  ((SP))
(PCl)  ((SP)+1)
(SP)  (SP) + 2

71. Simple Conditional Branches
8 Instructions where branch is based on “C/N/V/Z” bit clear/set
Most useful: branch if equal/not equal
More cycles if taken, less if not taken
Description
Assembly mnemonic
operation
Examples
Branch if no equal
Z =0
BNE rel8
LBNE rel16
if Z = 0
(PC)  (PC) + <rel8|rel16>
else
// No Nothing (effectively a NOP)
BNE label
LBNE label
Branch if equal
Z = 1
BEQ rel8
LBEQ rel16
if Z = 1
BEQ label
LBEQ label

72. More useful conditional branches (signed)
Usually we want to test for (=,<=,<,>,>=)
These instructions assumed signed numbers were subtracted
Description
Assembly mnemonic
operation
Examples
Branch if
greater than
Z + [N  V] = 0
BGT rel8
LBGT rel16
if [Z + [N  V] == 0]
(PC)  (PC) + <rel8|rel16>
else
// No Nothing (effectively a NOP)
BGT label
LBGT label
Branch if less than or equal to
Z + [N  V] = 1
BLE rel8
LBLE rel16
if [Z + [N  V] == 1]
BLE label
LBLE label
Branch if greater than or equal
[N  V] = 0
BGE rel8
LBGE rel16
if [[N  V] == 0]
BGE label
LBGE label
less than
[N  V] = 1
BLT rel8
LBLT rel16
if [[N  V] == 1]
BLT label
LBLT label

73. Derivation of Signed Conditionals

74. Derivation of Signed Conditionals
BLE condition
= Z + (N  V)
BGT condition
= (Z + (N  V))´
Greater than 0 -> 1
Everything else -> 0

75. Derivation of Signed Conditionals
BLT condition
= N´•V + N•V´
= N  V
BGE condition
= (N  V)´

76. More useful conditional branches (unsigned)
Description
Assembly mnemonic
operation
Examples
Branch if
higher than
C + Z = 0
BHI rel8
LBHI rel16
if [C + Z == 0]
(PC)  (PC) + <rel8|rel16>
else
// No Nothing (effectively a NOP)
BHI label
LBHI label
Branch if lower than or the same
C + Z = 1
BLS rel8
LBLS rel16
if [C + Z == 1]
BLS label
LBLS label
Branch if higher than or the same
C = 0
BHS rel8
LBHS rel16
if [C == 0]
BHS label
LBHS label
lower than
C = 1
BLO rel8
LBLO rel16
if [C = 1]
BLO label
LBLO label

77. Derivation of Unsigned Conditionals

78. Derivation of Unsigned Conditionals
BLS condition
= C + Z
BHI condition
= (C + Z)´
Greater than -> 1

79. Derivation of Unsigned Conditionals
BLO condition
= C
BHS condition
= C´

80. Signed vs. Unsigned Conditionals
Example: Difference between BGT and BHI
; signed conditional
LDAA #$01 ;interpret as +1
CMPA #$FF ;interpret as -1
BGT label ;branch taken
; unsigned conditional
LDAA #$01 ;interpret as 1
CMPA #$FF ;interpret as 25510
BHI label ;branch not taken

81. Bit Test and Branch
Branch or no branch?
MEM[100] =
BRCLR 100, , label
A: Take branch
B: Do not take branch 
Branch or no branch?
MEM[100] =
BRCLR 100, , label
A: Take branch
B: Do not take branch
Branch or no branch?
MEM[100] =
BRCLR 100, , label
A: Take branch
B: Do not take branch
Branch or no branch?
MEM[100] =
BRCLR 100, , label
A: Take branch 
B: Do not take branch
If all the high bits in the mask are 0 in memory, then branch
Description
Assembly mnemonic
operation
Examples
Branch if bits clear
BRCLR addr, mask8, rel8
if (addr) bitwise-AND mask8 == 0
(PC)  (PC) + <rel8|rel16>
else
// No Nothing (effectively a NOP)
BRCLR $50, 01,label
BRCLR 0,X,$FF,label
Branch if bits set
BRSET addr, mask8, rel8
if (addr)’ bitwise-AND mask8 == 0
BRSET $50, 01,label
BRSET 0,X,$FF,label
If all the high bits in the mask are 1 in memory, then branch

82. Register Test and Branch
Description
Assembly mnemonic
operation
Examples
Test Register and Branch if zero
TBEQ <ANY>, rel9
if [(r)== 0]
(PC)  (PC) + rel9
else
// No Nothing (effectively a NOP)
TBEQ label
TB label
Test Register and branch if not zero
TBNE <ANY>, rel9
if [(r) != 0]
BLE label
LBLE label

83. Increment/Decrement Register, Test for Zero and Conditionally Branch
Common set of operations: created 1 special instruction to do all of them at once
Any guess at when these are useful?
These are very useful for loops
Description
Assembly mnemonic
operation
Examples
Increment reg and branch if zero
IBEQ <ANY>, rel9
(<ANY>)  (<ANY>) + 1
if [(<ANY>) == 0]
(PC)  (PC) + rel9
IBEQ A, label
Increment reg and branch if not zero
IBNE <ANY>, rel9
if [(<ANY>) != 0]
IBNE X, label
Decrement reg and branch if zero
DBEQ <ANY>, rel9
(<ANY>)  (<ANY>) - 1
DBEQ SP, label
Decrement reg and branch if not zero
DBNE <ANY>, rel9
DBNE Y, label

84. Instruction Classes Data Transfer Arithmetic Group Logical
Transfer of control (branch/jump)
Machine Control
“Special”
Not universal and can be complex.
Will introduce as needed.