1. Using ISE WebPack for the second times
Project #2 : The Most Expensive Flip-Flop
Embedded and Digital Design
PENS-ITS
2014

2. Gambaran sistem Membuat lampu kedip ‘termahal’ counter n-bit 88 67
Clock 88 67
LED
2Hz
50MHz
FPGA

3. Counter n-bit, berapa-bit ?
Input 50MHz  output 2Hz
Dibagi
Didekati dengan 2n
225 =
50MHz : = Hz
25-bit !!

4. Alur disain

5. Nama, letak, dan top-level project
Buat project baru, File  New Project

6. Schematic

7. Synthesize, implement, generate

8. Reports

9. Download and Test Telah sesuai? Jika ya, katakan:
berhasil… berhasil… berhasil… hore!!!

10. Selesai Project #2 : The Most Expensive Flip-Flop Presented by
Riset Grup Embedded and Digital Design
PENS-ITS
2010