1. ISA - Instruction Set Architecture
Programmer’s Point of View
Copyright © Curt Hill

2. View point At this level we disregard the following important levels
Digital logic level
Micro-program level
Cache memory
Anything hidden in the CPU
Except as they impact the instructions
Only things that are of interest to the programmer
Copyright © Curt Hill

3. We are concerned with Memory models Registers
Number and type of registers
Some registers are hidden and so we can disregard
The IR is invisible to us
The PC may be accessible or not so we may have to consider it
The instructions, which is where we will spend the most time
Copyright © Curt Hill

4. Who uses this level? Machine language programmers
There are hardly any of these
Assembly language programmers
Even these are scarce but still viable
There is a one to one correspondence between machine and assembly language in most cases
Compilers
The compiler writer generates code very close to machine language code
Therefore the ISA must be well understood
Copyright © Curt Hill

5. Memory model issues Unit of addressability Alignment
Memory partitioning
Copyright © Curt Hill

6. Addressability What is the smallest unit that can be addressed? Bit
B1700 used a bit addressable scheme
Byte
Most machines are byte addressable
Word
A few are word addressable
When the word is short that is no problem
Copyright © Curt Hill

7. Examples 8080 had a 8 bit word 8086-80286 had a 16 bit word
Byte addressable or word addressable?
had a 16 bit word
Byte addressable
80386-Pentium had a 32 bit word
PDP-8 had a 12 bit word
IBM 360 had a 32 bit word
CDC Cyber had a 60 bit word
Word addressable
Copyright © Curt Hill

8. Alignment
Even in byte addressable machine there may be times when there is a requirement to align operands on boundaries
This is the issue of alignment
Are there ramifications of having any operand on any address?
Sometimes it is an error and sometimes it is a performance issue
Copyright © Curt Hill

9. Alignment Examples
IBM 360 required words to be on addresses divisible by 4
The successor IBM 370 dropped the requirement but the program ran faster if the alignment was maintained
PDP 11
16 bit word but byte addressable
had even and odd addresses
Pentiums have a 32 bit word but fetch things 64 bits at a time
They run faster if you waste a few bytes and align operands on addresses divisible by 8
What you especially want to avoid is a single reference that spans two double words
Copyright © Curt Hill

10. Partitioning memory
Some machines have a single address space which can contain data, instructions or whatever
Others partition the memory such that code goes in one part and data in another
This allows for a doubling of the address space since the context of the reference selects the memory
The Intel machines from 8086 up look like they partition memory but actually do not
Copyright © Curt Hill

11. Serialization
If two commands occur in sequence will they be executed sequentially? St 10,X -- store reg 10 to x L 5,X – load x into reg 5
This would assume that the load gets the contents saved by the store
Does that always happen?
Copyright © Curt Hill

12. Violation of serialization
In pipelined systems and some kinds of microprogramming this may not be the case
If you serialize memory references you slow performance
Or you may just specify that there may be a delay that is imposed on Stores
This makes the compiler writers job substantially more difficult, not to mention the assembler
Copyright © Curt Hill

13. Other topics Register types Instruction Format Addressing Modes
Assembly language programming
Copyright © Curt Hill