1. KLOE II Inner Tracker FEE
A multi-channels, low power, low noise device for KLOE II Inner Tracker RO
G. De Robertis1 F. Loddo1 A. Ranieri2
Servizio Elettronico sezione INFN di Bari
A. Balla3 M. Beretta1 G. Corradi3 P. Ciambrone1 G. Felici2 M. Flammia1 M. Gatta3
Servizio Elettronico Laboratori Nazionali di Frascati
1engineer 2physicist 3technician

2. KLOE II Inner Tracker FEE
Outline
KLOE II Inner Tracker FEE
Why a new readout device
Detector details
Readout requirements
Detector - FE integration
Front end
Device block diagram
Preamplifier-Shaper-discriminator
Digital section
Status & Future steps
GEM HVPS
Conclusions

3. Quads Quads Detector details (I)
Ultra-light device (kapton + support structure)
Detector - readout hard to integrate
Low gas gain device
High sensitivity head amplifier (few fC)
Inner Tracker placement
FEE power dissipation (~ 650 RO pitch  ~ 30 kchs)
In/Out signals
25 cm
10 cm
10 cm
DC wall
Quads
Quads
25 cm

4. + + Detector details (II) Readout pattern Cstrip max Cstrip min
Cin spread ~ 100 pF
Cstrip max
Cstrip min + +

5. Detector details (III)
Charge collection time
200 ns
2 s BX
KLOE DAQ timing
Lev1
2.2 s
Dead Time
 70 ns spread
 60 ns collection time
Typical case
 200 ns spread
Worst case
 200 ns collection time
Qmax = fC

6. Serial RO protocol (to reduce output channels)
Readout requirements
Serial RO protocol (to reduce output channels)
High modularity (64 channels)
Switched signals only while reading data
Asynchronous Trigger
Asynchronous RESET
200 ns
2 s BX
KLOE DAQ timing
Lev1
Dead Time

7. Device block diagram S C H M T A A R P S L I K N G Analog Digital Lev1
Common
Signals
Pre
A/S
Comp S H A P I N G M A S K
Reset
In 1
Global OR
Common ECS signals
Pre
A/S
Comp
In 64
Dedicated
RO Signals

8. Preamplifier-Shaper-Discriminator
CHARGE PREAMPLIFIER MAIN SPECS
Gain
5.6 mV/fC @ Cin = 0 pF
Linearity
< 1% ( fC range)
Noise (erms)
~ 450 e + 41 e/pF
Supply current
~ 110 A
a charge preamplifier to integrate the input strip current into a voltage 1
SHAPER MAIN SPECS
Gain 4
Linearity
< 3%
Supply current
~ 100 A
a shaper circuit providing noise filtering and semi-gaussian shaping 2
DISCRIMINATOR MAIN SPECS
Threshold fC
Offset (rms)
~ 2.2 mV
Supply current
~ 180 A 3
A leading-edge discriminator

9. 3 1 2 4 Digital Section DATA RO SECTION CONTROL SECTION Data Out
max 300 ns width 2
Data In
CONTROLLER
Ck (SC)
Discr 1
ONE SHOT S E R I A L Z
Reset
DAC Mon 4
Discr 64
ONE SHOT
ADC Mon
Ck(RO)
Lev 1
Pulse Odd
Pulse Even
Data (RO)
Mask
DATA RO SECTION
CONTROL SECTION

10. Input stage IA IB
Charge preamplifier based on improved cascode configuration
MOS in
gm(MOS in)  IMOS
Cascode gain  1/IB

11. Status & Future steps Design started on Nov 06 (AMS 0.35m tech)
16 Analog channels + 2 dummy channels
Complete digital section
Submitted on June 07
QFP80 package (24x16 mm2)
~ 3.2x2.6 mm2 die
1st stage
variable charge injection circuit
2st stage
new design
64 chs prototype
FUTURE STEPS

12. Detector - FE Integration
Input protection & strip reference network
Voltage Regulator
500 m pitch A S I C
650 m pitch
41.6 mm
500 m pitch ZIF connector
RO/parameter setting & Power
connector

13. G1 G2 G3 GEM HVPV CTRL Vmax -1200V Vmax -500V Vmax -700V Vmax -500V
Gnd Detector R

14. Conclusions
The Inner Tracker instrumentation is very challenging because the detector features (gain/placement/material)
A solution to connect FE boards to the readout electronics has been identified and will be used for the Inner Tracker prototype instrumentation
The design of a dedicated ASIC is going on. According to simulation the final 64 channels device should be characterized by low noise (450 erms + 41e/pF) and very low power dissipation (~ 150 mW)
A prototype (16 analog channels + full digital implementation) has been submitted to CMP. Some prototypes will be available in October.