1. P. Antonioli / INFN-Bologna
TOF readout
Reminder of TOF readout scheme and TOF readout modules
Overview of specifications with an emphasis on requirements for groups who want to use TOF electronis
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

2. P. Antonioli / INFN-Bologna
TOF readout reminder
18 TOF supermodules
Front-End cards with ASIC (NINO)
8 m
Rad-tolerance issues for electronics inside crates
Crates with HPTDC
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

3. TOF readout reminder (2)
6U depth x 9U height
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

4. P. Antonioli / INFN-Bologna
TRM reminder
684 Tdc Readout Module inside crates
HPTDC LUT
HPTDC
FIRMWARE
SRAM
FLASH
HPTDC LUT
INPUTS (LVDS)
TRG
Readout Controller
BOOT 32 mC
SEL WATCHDOG
x 15 L1
HPTDC
TRG
Output Fifo
VME Interface
INPUTS (LVDS) 32 32 32
x 15
VME bus 32
L2a
Event Manager
L2r 32
SRAM
Tested all components during 2004 irradiation campaigns 32
EVENT BUFFERS
Functionalities implemented by an FPGA
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

5. P. Antonioli / INFN-Bologna
Final TRM layout
To allow maintenance, easy mounting operation and matching with front end, HPTDC mounted on 24 ch piggy back
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

6. P. Antonioli / INFN-Bologna
Final TRM layout (2)
6U MB prototype housing 2 PB
5 piggyback cards per side, 1 central PCB for FPGAs and memories, central aluminium bar for heat dissipation
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

7. Radiation levels reminder
Radiation levels expected at ALICE/TOF:
1.2 Gy/10 years (TID)
Total neutron fluence (>20 MeV): /cm2/10 years.
Total charged hadrons (>20 MeV): /cm2/10 years.
89 Hz/cm2 expected in PbPb MB events (hadrons+neutrons > 20 MeV).
For ALICE/TOF careful design needed to handle SEU,
Degradation for TID effects neglectable.
Latchup protections needed.
Some specifications modified in 2004 due to the need to implement radiation tolerant electronics.
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

8. P. Antonioli / INFN-Bologna
DRM reminder
Tasks:
Read data on VME backplane (from TRM)
Send data to central Alice DAQ through DDL
Provide interface with trigger (TTC)
Provide Slow Control function/access to VME
Actel reprogramming
Work done during 2004:
Developed and tested DDL interface
Developed and tested TTC interface
Radiation test to check various slow control solutions
On-going definition of crate/TRM specifications following tender won by CAEN and impacting on DRM specs.
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

9. Final DRM scheme TTCrx DDL SIU Readout VME interface
FPGA: Actel ProAsic+
DDL SIU
FIRMWARE
FLASH
VME bus
SRAM
EVENT BUFFERS
VME ACCESS
BOOT mC
SEL WATCHDOG
Optical link to PC (PCI bus)
Slow control access
FPGA: Actel ProAsic+
ARM
(Actel reprogramming)
Eth0/ Slow Control backup
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

10. P. Antonioli / INFN-Bologna
How we arrived here...
The use of new DDL-D-RORC cards (with two optical links each) allows to avoid master/slave scheme between the two crates, simplifying our design (decision taken March ’04, without any impact on foreseen costs) and making readout much more robust (every crate is “independent”). NOT RELEVANT FOR T0
DDL integration tested with DRM prototype card (Dec ’03/Jan ’04)
TTC integration tested (July ’04) with DRM prototype card + TTCvi/TTCex + LTU (Sep/Oct ’04)
Tests done for TRM emphasized rad-tol problems with Altera FPGAs. Need to move FPGA TRM (now Actel) reprogramming to DRM
(this makes DRM/TRM specifications much more interconnected)
PowerPC from Artesyn as slow control solution successfully tested in magnetic field (Dec ’03), but not encouraging test in radiation (PSI/May ’04). Looked for a different solution. Optical link tested in radiation.
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

11. P. Antonioli / INFN-Bologna
Rad tests and FPGA...
PSI May & June ’04: Altera Stratix, Flash, RAM, mC, low-drop, current limited p-switch, PowerPC
LNL July ’04: HPTDC with heavy ions
CRC/Louvain Nov ’04: optical link and ARM processor
Assessed SEU rates for almost all components (not discussed here, see LECC2004 paper). Stratix for TRM is not a viable option.
Moved to reprogrammable Flash based FPGA (Actel ProAsic Plus) [rad tests in ALICE and LHCb ok)
BUT: Additional logic needed to support Actel reprogramming
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

12. P. Antonioli / INFN-Bologna
Actel reprogramming
Due to the technology inherently more robust (Flash vs RAM) configuration upset absent.
Need of special voltages during reprogramming: +16.2, V
Configuration is not simply a matter of handlong a download through a passive serial Flash, but the firmware code needs to be interpreted while downloading (RAM also needed for staging)
We added 2 power supply (x crate) providing and V (we will use +/- 12 V pins).
We wil use one external (to the TRM) mC and use JTAG on the backplane (MTM bus on VME64X)
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

13. Actel reprogramming (2)
High integration needed
Prescriptive steps to start reprogramming (power up / addressing / etc)
Crate VME ... Now not so standard!
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

14. Move slow control outside
The “big” change is related to the choice of the slow control/configuration solution: we move outside the “intelligent” part (18 PC in control room, each connected to 4 crates).
Optical PCI-VME adapters commercially available. Make it rad-tolerant implementing FPGA with Actel + use serializer/deserializer tested in radiation
[successfully tested at Louvain in Nov. ’04]
V2718 from CAEN
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

15. P. Antonioli / INFN-Bologna
VME mastering
Test carried out jointly with CAEN
Modified firmware of their VME Master (V1718/V2818/A2818).
FPGA initiating VME cycles when in DAQ mode
(end Oct ’04)
250 ns!
Trigger DS
DTACK
CDM prototype
HPTDC
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

16. P. Antonioli / INFN-Bologna
CPDM
Clock and pulser distribution module
- Hosted only in one crate every two
- “simple” but “delicate” card
No VME interface required, latch-up protections as for TRM/DRM/LTM
- tests carried out to check clock jitter of present clock distribution scheme
defined clock cable and connectors
- the pulser section of this card is not relevant for T0
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

17. Clock Distribution tests
Over 16 channels tested in optical fan-out jitter always well below 15 ps
Opt.rec/LVDS adaptation ok.
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

18. Clock jitter and distribuition
Over 16 channels tested in optical fan-out jitter always well below 15 ps
Opt.rec/LVDS adaptation ok.
Tyco: CPDM side
Defined high quality clock cable and connectors for distribution from CPDM to TRM/DRM/LTM,
Tripolar connectors (including shield) from Tyco (CPDM) and Fischer
Fischer: TRM side
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

19. P. Antonioli / INFN-Bologna
P2 bus
Through P2 main synch and trigger signals distributed to TRMs.
All signals LVTTL (the most time critical ones “LVTTL differential”)
DRDY and BUSY for readout.
ON/FAULT signals for control.
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

20. Guidelines for TRM users
Questions:
48 channels leading edge only
96 channels after your charge to time converter
correct?
others?
About demultiplexing story:
Working in VHRM, leading edge only, 4 channels/HPTDC maximum bandwidth: 5 MHz (which is different from dead-time and different from buffer occupancy).
T0 needs 156 ch, but with only 4 ch/HPTDC,
so T0 needs two TRMs
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

21. P. Antonioli / INFN-Bologna
Guidelines for TRM (2)
Input signals must be LVDS
We use VHDCI connectors, with custom pin-out, 24 pairs per cable.
We use Amphenol Skewclear cables.
Tested up to 7 m, using NINO as LVDS driver.
Please check carefully cable length and your LVDS driver.
You will need at least 156/12=13 cables (you will use one signal every 2)
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

22. P. Antonioli / INFN-Bologna
Guidelines for TRM (3)
Data are matched on L1 and moved in memory buffers, waiting for L2a. TRM memory size (512 kB) designed for Pb/Pb TOF occupancy and 240 channels/TRM. Please check if it is ok for your need.
In principle T0 doesn’t need CPDM but you need to provide to the 2 TRMs and 1 DRM, high quality LHC clock in LVDS standard, using the Fischer tripolar connector.
Our suggestion: use our CPDM. You need to bring to the CPDM LHC clock with unimodal fibre (could be interesting to send it from the same optical fan-out used for TOF crates).
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

23. P. Antonioli / INFN-Bologna
Guidelines for crates
DRM
T0 crate:
CPDM
TRM
TRM
Please consider the following (just to use the crate as it is):
such a system needs water (but we should test if it is really necessary: just 4 cards over 12, and you can put fans around);
you need also a PC with optical link to handle the SCL
through a branch controller we power (48 V) and control LV (and ON/FAULT pins) of each card (could be managed by TOF directly but we must check cables, etc.). Communication through an OPC server (or may be TCP-IP/DIM interface to PVSS). To be checked if you can simply connect to our LV system
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

24. Guidelines for crates (2)
If T0 wants to add other cards to the crate:
- Do not put other VME masters inside, don’t use BR lines
Note voltages: 3.3 V only (even on 5 V pins) and +16.2/-13,5 V (normally not available) on +12/-12V pins
You need to use cardlok. No “guides”.
Don’t interfere with P2 bus (rows A-C strictly defined) and implement ON/FAULT signals
Please note distance of P1 from bottom is not standard + 6Ux9U format (not P3, P1 in the middle) + VME64X connectors
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

25. P. Antonioli / INFN-Bologna
Conclusions
Working out the TOF readout project, precise specifications now have been elaborated. Unfortunately (essentially for radiation tolerance and magnetic field issues) crates are not so standard as we originally hoped.
T0 is welcome to use our readout electronics, but please be aware of specifications to be followed and the need for deployement near T0 electronics.
Please be in touch with us, especially consider we don’t have spares for T0 and specific orders must be put in place (funding to be defined)!
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

26. DDL integration reminder
(results already presented at CR4/March 2004)
Bandwidth of MB/s with fixed packet size of 2 – 5 kB
DATE Version 4.7, Readout Version 4.6
Event rate up to 330 Hz
No errors over 60 M events
DRM prototype with DDL SIU
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna

27. TTC integration reminder
TTCrm mounted on DRM prototype
TTCvi
TTCex
Tested decoding of L1/L2 messages
Tested LTU (received at October)
No problem foreseen
Trigger distribution
to HPTDC cards
HPTDC cards
10/12/2004 T0/V0 meeting
P. Antonioli / INFN-Bologna