1. Analog and digital electronics

2. Field Effect Transistors, Introduction to Operational Amplifier Operational, Amplifier Application Circuits
Module-1

3. Referred Books
Anil K Maini, Varsha Agarwal : Electronic Devices and Circuits, 2012.
Robert L. Boylestad Louis Nashelsky : Electronic Devices and Circuit Theory, Eleventh Edition, 2013.
Albert Malvino, David J. Bates : Electronic principles, Eighth edition, 2016.

4. Objectives Types of FETs:
JFETs and MOSFETs, Construction and operation of JFETs , Construction and operation of MOSFETs, Comparison between JFETs and MOSFETs, Biasing of the MOSFETs, Introduction to CMOS.
Multivibrator circuits configuration around digital integrated circuits,
Multivibrator circuits configured around timer IC 555.
OP-Amp
Difference between an ideal and practical opamp Peak Detector Circuit, Absolute Value Circuit Comparator, Active Filters, Phase Shifters Non-Linear Amplifier, Relaxation Oscillator Current-To- Voltage Converter, Voltage-To-Current Converter, Sine Wave Oscillators.

5. Field Effect Transistors

6. Introduction
The primary difference between the Transistor and JFET is that the BJT transistor is a current-controlled device where as while the JFET transistor is a voltage-controlled device.

7. Introduction
In other words, the current IC is a direct function of the level of IB.
For the FET the current ID will be a function of the voltage VGS applied to the input circuit.
In each case the current of the output circuit is being controlled by a parameter of the input circuit in one case a current level and in the other an applied voltage.

8. Introduction Advantages of FET Very high input impedance (109-1012Ω)
Source and drain are interchangeable
Low Voltage Low Current Operation is possible (Low- power consumption)
Less Noisy
No minority carrier storage (Turn off is faster)
Very small in size, occupies very small space in ICs

9. Types of Field Effect Transistors (The Classification)
n-Channel JFET
p-Channel JFET
FET
FET
FET
FET
FET
JFET
MOSFET (IGFET)
Enhancement MOSFET
Depletion MOSFET
n-Channel EMOSFET
n-Channel DMOSFET
p-Channel DMOSFET
p-Channel EMOSFET

10. Junction Field Effect Transistors
JFET is three terminal device where the voltage applied at one terminal controls the current through the other two terminal.
JFET is comprise a semiconductor channel which is path for flow of current.
Two types of channel: P-Type and N-Type

11. Junction Field Effect Transistors Construction

12. Junction Field Effect Transistors Construction
Construction (Animation)
Drain
N-Channel
Gate
P-type
Semiconductor
N-type
Semiconductor
Depletion
Layer
Source

13. Junction Field Effect Transistors Construction

14. Junction Field Effect Transistors Construction
The n -type material, which forms the channel between the embedded layers of p -type material.
The top of the n -type channel is connected through an ohmic contact to a terminal referred to as the drain (D), whereas the lower end of the same material is connected through an ohmic contact to a terminal referred to as the source (S).
The two p -type materials are connected together and to the gate (G) terminal.
In the absence of any applied potentials the JFET has two p – n junctions under no-bias conditions.

15. Junction Field Effect Transistors Principal of Operation: N-Channel JFET

16. Junction Field Effect Transistors Principal of Operation: N-Channel JFET
VGS=0V, VDS=Some Positive Value
VDS is applied across the channel and the gate is connected directly to the source to establish the condition VGS=0 V. The result is a gate and a source terminal at the same potential and a depletion region in the low end of each p material.

17. Junction Field Effect Transistors Principal of Operation: N-Channel JFET
The instant the voltage VDD (=VDS) is applied, the electrons are drawn to the drain terminal, establishing the conventional current ID.
The path of charge flow clearly reveals that the drain and source currents are equivalent (ID = IS).
The flow of charge is relatively outgoing and is limited solely by the resistance of the n -channel between drain and source.

18. Junction Field Effect Transistors Principal of Operation: N-Channel JFET
As the voltage VDS is increased from 0 V to a few volts, the current will increase (ohms Law) and the plot of ID versus VDS will appear as shown below.
The relative straightness of the plot reveals that for the region of low values of VDS , the resistance is essentially constant.
As VDS increases and approaches a level referred to as VP, the depletion regions will widen, causing a noticeable reduction in the channel width.
The reduced path of conduction causes the resistance to increase and the horizontal curve to occur.

19. Junction Field Effect Transistors Principal of Operation: N-Channel JFET
If VDS is increased to a level where it appears that the two depletion regions would “about to touch” as shown in Fig, a condition referred to as pinch-off will result.
The level of VDS that establishes this condition is referred to as the pinch-off voltage and is denoted by VP.

20. Junction Field Effect Transistors Principal of Operation: N-Channel JFET
The term pinch-off is a contradiction in that it suggests the current ID is pinched off and drops to 0A, but its not.
In reality a very small channel still exists, with a current of very high density. The fact that ID does not drop off at pinch-off and maintains the saturation level and it called IDSS is drain-to-source current with a short-circuit connection from gate to source.

21. Junction Field Effect Transistors Principal of Operation: N-Channel JFET
VGS < 0V
The VGS is the control voltage for JFETs in the same way as the IB is for BJTs.
When VGS is negative the depletion region is increases, so the pinch off occurs at lower value of VDS, as effect the IDSS is also decreases.
Further VGS is made more negative then the IDSS decreases and ID current becomes zero for VGS=-VP. This voltage is referred as gate- source cut off voltage VGS(off).
Next slide shows the output characteristic curve.

22. Junction Field Effect Transistors Principal of Operation: N-Channel JFET
Output characteristic curve

23. Junction Field Effect Transistors Principal of Operation: N-Channel JFET
The ohmic or voltage-controlled resistance region. In this region the JFET can actually be employed as a variable resistor whose resistance is controlled by the applied gate-to-source voltage.
So the drain resistance rd in the saturation region is given by the following equation:
where ro is the resistance with VGS=0V and rd is the resistance at a particular level of VGS.
The relation between the output current ID in the saturation region for a given value of input VGS is given by:

24. Junction Field Effect Transistors Principal of Operation: N-Channel JFET
Transfer Characteristic curve of N-Channel JFET

25. Junction Field Effect Transistors Principal of Operation: P-Channel JFET
The VGS is positive for P-Channel JFET.
The below figure the characteristic curve of P- Channel JFET.

26. Junction Field Effect Transistors Effect of Temperature on JFET Parameters
Better thermal stability
Positive temperature coefficient: Increases in JFET temperature results in decrease in the depletion region width and decrease in the carrier mobility which leads to increase in ID.
Decrease in carrier mobility gives ID a negative temperature coefficient.

27. MOSFET
Metal –oxide– semiconductor field effect transistor also referred as insulated-gate FET (IGFET)
MOSFETs are further classified into depletion type (D-MOSFET or DE-MOSFET) and enhancement type (E-MOSFET)

28. DE-MOSFET
Construction

29. DE-MOSFET
Symbols

30. DE-MOSFET N-Channel Construction (Animation) SiO2 Metal Contact
Drain N
P-Type Substrate N
Gate
Substrate
Source N

31. N- Channel DE-MOSFET Operation:
The gate-to-source voltage is set to 0V by the direct connection from one terminal to the other, and a voltage VDD is applied across the drain-to- source terminals.

32. N- Channel DE-MOSFET Operation
The result is an attraction of the free electrons of the n- channel for the positive voltage at the drain.
The result is a current similar to that flowing in the channel of the JFET.
In fact, the resulting current with VGS=0V continues to be IDSS.

33. N- Channel DE-MOSFET
Characteristics Curve

34. N- Channel DE-MOSFET VGS < 0V (negative voltage)
The negative potential at the gate will tend to pressure electrons toward the p -type substrate (like charges repel) and attract holes from the p -type substrate (opposite charges attract).
Depending on the magnitude of the negative bias established by VGS , a level of recombination between electrons and holes will occur that will reduce the number of free electrons in the n -channel available for conduction. The more negative the bias, the higher is the rate of recombination.
The resulting level of drain current is therefore reduced with increasing negative bias for VGS till reaches to the pinch-off voltage.
The resulting levels of drain current and the plotting of the transfer curve proceed exactly same as the JFET.

35. P- Channel DE-MOSFET
The construction of a p- channel depletion-type MOSFET is exactly the reverse of N-Channel DE- MOSFET.
The terminals remain as identified, but all the voltage polarities and the current directions are reversed, as shown in the same figure.

36. P- Channel DE-MOSFET
Transfer characteristics

37. E-MOSFET Construction
The absence of a channel between the two n or p doped regions.

38. E-MOSFET
Symbol

39. N-Channel E-MOSFET Operation VGS=0 V
A voltage applied between the drain and the source of the device of the absence of an n -channel (with its generous number of free carriers) will result in a current of effectively 0A — quite different from the depletion-type MOSFET and JFET, where ID=IDSS.
It is not sufficient to have a large accumulation of carriers (electrons) at the drain and the source (due to the n -doped regions) if a path fails to exist between the two.
VGS< 0 V (Negative Voltage)
Same as when VGS=0 V

40. N-Channel E-MOSFET VGS>0 V (Positive Voltage)
The positive potential at the gate will pressure the holes (since like charges repel) in the p –substrate.
The electrons in the p-substrate (the minority carriers of the material) will be attracted to the positive gate and accumulate in the region near the surface of the SiO2 layer.
As VGS increases in magnitude, the concentration of electrons near the SiO2 surface increases until eventually the induced n-type region can support a measurable flow between drain and source.
The level of VGS that results in the significant increase in drain current or minimum voltage to create channel between drain and source is called the threshold voltage and is given the symbol VT .

41. N-Channel E-MOSFET
As VGS is increased beyond the threshold level, the density of free carriers in the induced channel will increase, resulting in an increased level of drain current.
However, if hold VGS constant and increase the level of VDS , the drain current will eventually reach a saturation level as occurred for the JFET and depletion-type MOSFET.
The leveling off of ID is due to a pinching-off process depicted by the narrower channel at the drain end of the induced channel as shown in Fig.

42. N-Channel E-MOSFET
Transfer characteristics

43. N-Channel E-MOSFET
Saturation level for VDS is related to the level of applied VGS by
VDS(sat) = VGS - VT
For values of VGS less than the threshold level, the drain current of an enhancement type MOSFET is 0mA.
For levels of VGS > VT, the drain current is related to the applied gate-to-source voltage by the following nonlinear relationship:
ID = k(VGS - VT)2
The k term is a constant that is a function of the construction of the device. The value of k can be determined from the following equation:
where ID(on) and VGS(on) are the values for each at a particular point on the characteristics of the device.

44. Differences between JFETs and MOSFETs
Operate only in depletion mode
Operate in both depletion and enhancement mode
Low input resistance (> 109Ω)
High input resistance (around 1013Ω)
High drain resistance
Low drain resistance
Large Leakage current
Small Leakage current
Not easy Construction
Easy Construction

45. Biasing MOSFETs Biasing DE-MOSFET Biasing E-MOSFET
Fixed Bias Configuration
Self Bias Configuration
Voltage Divider Bias Configuration
Biasing E-MOSFET
Feedback Bias Configuration
The general relationships that can be applied to the dc analysis of all FET amplifiers are
IG ≅ 0A
and
ID = IS
For JFETS and depletion-type MOSFETs ID is given by:
For Enhancement-type MOSFETs ID is given by:

46. Biasing MOSFETs DE-MOSFET Fixed Bias Configuration
AC Circuits
DC Circuits

47. Biasing MOSFETs DE-MOSFET Fixed Bias Configuration
DC Analysis:
Apply KVL at input side
– VGG –IGRG – VGS=0
As IG=0A
We can write VGS= – VGG
and
Apply KVL at Output side
VDD – IDRD – VDS=0
So VDS= VDD – IDRD

48. Biasing MOSFETs DE-MOSFET Fixed Bias Configuration
Problem:
Refer Solved Problems from Text Book

49. Biasing MOSFETs DE-MOSFET Self Bias Configuration
AC Circuit
DC Circuit

50. Biasing MOSFETs DE-MOSFET Self Bias Configuration
DC Analysis:
From circuit IS=ID
Apply KVL at input side
–IGRG – VGS – ISRS=0
As IG=0A
We can write VGS= ISRS = IDRS
and
Apply KVL at Output side
VDD – IDRD – VDS – ISRS =0
So we can write VDS= VDD – ID(RD+RS)

51. Biasing MOSFETs DE-MOSFET Voltage-Divider Bias Configuration
AC Circuit
DC Circuit

52. Biasing MOSFETs DE-MOSFET Voltage-Divider Bias Configuration
DC Analysis
From thevinin’s theorem
The gate-source voltage is
VGS = VG – VS = VG – IDRS
The drain current is
Apply KVL at Output side
VDD – IDRD – VDS – ISRS =0
So we can write VDS= VDD – ID(RD+RS)

53. Biasing MOSFETs DE-MOSFET Voltage-Divider Bias Configuration
Problem:
Design a voltage divider bias network using DE- MOSFET with supply voltage VDD=16V, IDSS=10mA and VP= - 5V to have a quiescent drain current of 5mA and gate voltage of 4V. Assume the drain resister RD to be four times the source resistor RS.

54. Biasing MOSFETs E-MOSFET Feedback Bias Configuration
AC Circuit
DC Circuit

55. Biasing MOSFETs E-MOSFET Feedback Bias Configuration
DC Analysis
As IG=0A and
Apply KVL at input side
VDD= IDRD+RGIG+VGS
VDD= IDRD+VGS
So VGS= VDD – IDRD
Apply KVL at output side
VDD= IDRD+VDS
So VDS= VDD – IDRD

56. Biasing MOSFETs E-MOSFET Feedback Bias Configuration
Problem:
The levels of VDS and ID are specified as VDS=½VDD, VGS = VGS(on) and ID = ID(on) for the network shown below. Determine the levels of VDD and RD .

57. Biasing MOSFETs E-MOSFET Voltage Divider Bias Configuration
AC Circuit
DC Circuit

58. Biasing MOSFETs E-MOSFET Voltage Divider Bias Configuration
DC Analysis
From thevinin’s theorem
The gate-source voltage is
VGS = VG – VS = VG – IDRS
The drain current is
Apply KVL at Output side
VDD – IDRD – VDS – ISRS =0
So we can write VDS= VDD – ID(RD+RS)

59. FET Applications
Because of the extremely high input impedance of a JFET compared to BJT so it is used as input amplifier in oscilloscope, electronic voltmeter, measuring instruments etc. Typical application as follows:
Amplifier
Analog Switch
Multiplexer
Current Limiter
Voltage Variable Resistor (VVR)

60. FET Applications- Amplifier
FET used as low noise amplifier (Common Source) and buffer amplifier (Common Drain).
Low Noise Amplifier:
Its used as front end of the receiver and in other electronic equipment's.
Buffer Amplifier:
It offers high input impedance and low output impedance so used as buffer amplifier to isolate the preceding stage from the following stage.

61. FET Applications- Analog Switch
In this application, the JFET acts as a switch that either transmits or blocks a small ac signal.
To get this type of action, the gate-source voltage VGS has only two values: either zero or a negative voltage. In this way, the JFET operates either in the saturation region or in the cut-off region.
When VGS=0V, then FET operates in saturation region and acts as closed switch.
When VGS < 0V, then FET operates in cut-off region and acts as open switch.

62. FET Applications- Multiplexer
Multiplex means “many into one.” Figure shows an analog multiplexer, a circuit that steers one or more of the input signals to the output line. Each JFET acts like a series switch.
The control signals (V1, V2, and V3) turn the JFETs on and off.
When a control signal is high, its input signal is transmitted to the output.
For instance, if V1 is high and the others are low, the output is a sine wave. If V2 is high and the others are low, the output is a triangular wave. When V3 is the high input, the output is a square wave.
Normally, only one of the control signals is high; this ensures that only one of the input signals is transmitted to the output.

63. FET Applications- Current Limiter
In this application, the JFET operates in the ohmic region rather than the active region.
If the load becomes shorted load usually produces an excessive current. But with the JFET in series with the load, the current is limited (max IDSS) to a safe value, as JFET operate in Saturation Region.

64. FET Applications- Voltage Variable Resistor (VVR)
The JFET is as a variable resistor whose resistance value is controlled by the applied dc voltage at the gate terminal in ohmic region.
The resistance RD can be controlled by VGS.
From figure we can observe that as VGS increases the RD also increases, this phenomenon is called VVR.

65. CMOS Devices
Complementary MOSFET

66. CMOS Devices Complementary MOSFET
It has extensive applications in computer logic design. The relatively high input impedance, fast switching speeds, and lower operating power levels.
Both P-type and N-Type E-MOSFET are diffused onto the same chip.
One very effective use of the complementary arrangement is as an inverter, as shown in previous slide.
As introduced for switching transistors, an inverter is a logic element that “inverts” the applied signal. That is, if the logic levels of operation are 0 V (0-state) and 5 V (1-state), an input level of 0 V will result in an output level of 5 V, and vice versa.

67. CMOS Devices Circuit operate as follows:
When Vi=0V (Low) the Q2=ON and Q1=OFF, so the VO= VSS (High).
When Vi=5V (High) the Q2=OFF and Q1=ON, so the VO= 0V (Low).

68. Introduction to Operational Amplifier

69. Introduction to Operational Amplifier Ideal v/s practical Op-amp
Early operational amplifiers (op-amps) were used primarily to perform mathematical operations such as addition, subtraction, integration, and differentiation - thus the term operational.
The standard operational amplifier (op-amp) symbol is shown in below

70. Introduction to Operational Amplifier Ideal v/s practical Op-amp
The electric equivalent model of Practical Op-Amp + – vo
vi2
vi1 Ri
AOLvd Ro vd

71. Introduction to Operational Amplifier Ideal v/s practical Op-amp
The electric equivalent model of Ideal Op-Amp + – vo
vi2
vi1
AOLvd vd
For Ideal Op-Amp
Infinite input resistance (Ri)
Zero output resistance (Ro)

72. Introduction to Operational Amplifier Ideal v/s practical Op-amp
Difference between Ideal and Practical Op-Amp
Parameters
Ideal Op-Amp
Practical Op-Amp
(E.g. LM 741)
Bandwidth (BW)
Infinite
1MHz
Slew Rate (SR)
0.5 V / μs
Open loop gain (AOL)
200,000
Common Mode Rejection Ratio (CMRR)
90 dB
Power Supply Rejection Ratio (PSRR)
Zero
120 dB (+Supply)
110 dB (-Supply)
Input impedance (Ri)
2 MΩ
Output impedance (Ro)
75 Ω
Offset and Offset Drifts
1mV, 20nA

73. Introduction to Operational Amplifier
The 741 Op Amp

74. Introduction to Operational Amplifier Performance Parameters
Key op-amp parameters includes the following:
Bandwidth (BW)
Slew Rate (SR)
Open loop gain (AOL)
Common Mode Rejection Ratio (CMRR)
Power Supply Rejection Ratio (PSRR)
Input impedance (Ri)
Output impedance (Ro)
Settling time
Offset and Offset Drifts

75. Introduction to Operational Amplifier Performance Parameters
Bandwidth (BW)
An ideal operational amplifier has an infinite frequency response and can amplify any frequency signal from DC to the highest AC frequencies so it is therefore assumed to have an infinite bandwidth.
With real op-amps, the bandwidth is limited by the Gain-Bandwidth product (GB), which is equal to the frequency where the amplifiers gain becomes unity.
The 741C has an open-loop voltage gain of 100,000, equivalent to 100 dB. Since the open-loop cutoff frequency is 10 Hz, the voltage gain breaks at 10 Hz and then rolls off at a rate of 20 dB per decade until it is 0 dB at 1MHz.

76. Introduction to Operational Amplifier Performance Parameters
Slew Rate (SR):
The slew rate represents the fastest response that an op amp can have.
Slew rate equals the change in output voltage divided by the change in time.
For example, the slew rate of a 741C is 0.5 V/μs. This means that the output of a 741C can change no faster than 0.5 V in a microsecond.

77. Introduction to Operational Amplifier Performance Parameters
Open loop gain (AOL):
When no feedback path (or loop) is used, the voltage gain is maximum and is called the open-loop voltage gain, designated AOL.
The open-loop voltage gain, AOL, of an op-amp is the internal voltage gain of the device and represents the ratio of output voltage to input voltage when there are no external components.
The open-loop voltage gain is set entirely by the internal design. Open-loop voltage gain can range up to 200,000 (106 dB).

78. Introduction to Operational Amplifier Performance Parameters
Common Mode Rejection Ratio (CMRR):
The ratio of differential gain to common-mode gain in an amplifier. It is a measure of the ability to reject a common-mode signal and is usually expressed in decibels.
The measure of an amplifier’s ability to reject unwanted signal.
Ideally, an op-amp provides a very high gain for differential-mode signals and zero gain for common-mode signals.
Practical op-amps, however, do exhibit a very small common-mode gain (usually much less than 1), while providing a high open-loop differential voltage gain (usually several thousand).
The higher the open-loop gain with respect to the common-mode gain, the better the performance of the op-amp in terms of rejection of common-mode signals.

79. Introduction to Operational Amplifier Performance Parameters
Power Supply Rejection Ratio (PSRR):
The PSRR is equals the change in the power supply voltage to corresponding change in the output voltage.
E.g. PSRR = 158 µV/V. This tells, a change of 1 V in the supply voltage will produce a change in the input offset voltage of 158 µV.

80. Introduction to Operational Amplifier Performance Parameters
Input impedance (Ri):
It is the impedance looking into the input terminal of the opamp.

81. Introduction to Operational Amplifier Performance Parameters
Output impedance (Ri):
It is the impedance looking into the output terminal of the opamp and ground.

82. Introduction to Operational Amplifier Performance Parameters
Settling time (tS):
Settling time is the time it takes for an op-amp to settle to achieve the specified accuracy at the output.
It is strongly dependent on the circuit components in the signal and feedback paths (resistors, capacitors, inductors).

83. Introduction to Operational Amplifier Performance Parameters
Offset and Offset Drifts:
A diff amp has input bias and offsets that produce an output error when there is no input signal.
In many applications, the output error is small enough to ignore.
But when the output error cannot be ignored, a designer can reduce it by using equal base resistors. This eliminates the problem of bias current, but not the offset current or offset voltage.
For the 741 opamp input bias current is of 80 nA, input offset current of 20 nA and an input offset voltage of 2 mV

84. Operational Amplifier Application Circuits

85. Peak Detector Circuit
RC ≥ 10 T

86. Peak Detector Circuit
During +ve half cycle when the input voltage is positive, the diode is conducting/ON and capacitor charges to the peak of the input voltage.
Second, when the input voltage is negative during –ve half cycle, the diode is non-conducting/OFF and the capacitor discharges through the load resistor.
As long as the discharging time constant is much greater than the period of the input signal (T), the output voltage will be approximately equal to the peak value of the input voltage.
This can achieved by making discharging time constant RC can be made much longer than the period of the input signal (RC ≥ 10 T), will get almost perfect peak detection of low-level signals.
If the peak-detected signal has to drive a small load, to avoid loading effects by connecting the voltage follower (op-amp buffer) isolates the small load resistor from the peak detector. This prevents the small load resistor from discharging the capacitor too quickly.

87. Comparator
Comparator circuit compares a single voltage on one input of op-amp with a known voltage called reference voltage (Trip point or trigger point) on the other input and produces high or low output depending upon relative magnitude of two input.
Comparators with Zero Reference
Comparators with Nonzero References
Comparators with Hysteresis or Schmitt Trigger
Window Comparator

88. Comparator Comparators with Zero Reference
Non-Inverting Comparator
Because of the high open-loop voltage gain, a positive input voltage produces positive saturation, and a negative input voltage produces negative saturation.
Above circuit is called a zero-crossing detector because the output voltage ideally switches from low to high or vice versa whenever the input voltage crosses zero (input compares with zero reference voltage).

89. Comparator Comparators with Zero Reference
Non-Inverting Comparator

90. Comparator Comparators with Zero Reference
Inverting Comparator
The input signal drives the inverting input of the comparator. In this case, a positive input voltage produces a maximum negative saturation, as shown in above diagram. On the other hand, a negative input voltage produces a maximum positive saturation.

91. Comparator Comparators with Zero Reference
Inverting Comparator

92. Comparator Comparators with Nonzero References
Non-Inverting Comparator: Positive reference
When Vin is greater than Vref, the differential input voltage is positive and the output voltage is high (+Vsat). When Vin is less than Vref, the differential input voltage is negative and the output voltage is low (-Vsat).
Vin > Vref then Vout = +Vsat
Vin < Vref then Vout = - Vsat

93. Comparator Comparators with Nonzero References
Non-Inverting Comparator: Positive reference

94. Comparator Comparators with Nonzero References
Non-Inverting Comparator: Negative reference
Vin > Vref then Vout = + Vsat
Vin < Vref then Vout = - Vsat

95. Comparator Comparators with Nonzero References
Non-Inverting Comparator: Negative reference

96. Comparator Comparators with Hysteresis or Schmitt Trigger
If the input to a comparator contains a large amount of noise, the output will be erratic when Vin is near the trip point.
When the noise peaks are large enough, they produce unwanted changes in the comparator output. In diagram observe that producing unwanted transitions from low to high. When an input signal is present, the noise is superimposed on the input signal and produces erratic triggering.
One way to reduce the effect of noise is by using a comparator with positive feedback.
The positive feedback produces two separate trip points that prevent a noisy input from producing false transitions.

97. Comparator Comparators with Hysteresis or Schmitt Trigger
Inverting Schmitt trigger
When the comparator is positively saturated, a positive voltage is fed back to the noninverting input. This positive feedback voltage holds the output in the high state.
Similarly, when the output voltage is negatively saturated, a negative voltage is fed back to the noninverting input, holding the output in the low state.

98. Comparator Comparators with Hysteresis or Schmitt Trigger
Inverting Schmitt trigger

99. Comparator Comparators with Hysteresis or Schmitt Trigger
Inverting Schmitt trigger

100. Comparator Comparators with Hysteresis or Schmitt Trigger
Inverting Schmitt trigger
The output voltage will remain in a given state until the input voltage exceeds the reference voltage for that state.
For instance, if the output is positively saturated, the reference voltage is +BVsat. The input voltage must be increased to slightly more than +BVsat to switch the output voltage from positive to negative, as shown in input/output response has hysteresis.
Once the output is in the negative state, it will remain there indefinitely until the input voltage becomes more negative than -BVsat. Then, the output switches from negative to positive shown in input/output response has hysteresis.

101. Comparator Comparators with Hysteresis or Schmitt Trigger
Inverting Schmitt trigger
The trip points are defined as the two input voltages where the output voltage changes states. The upper trip point (UTP) has the value:
UTP = + BVsat
and the lower trip point (LTP) has the value:
LTP = - BVsat
The difference between these trip points is defined as the hysteresis (also called the deadband ):
VH = UTP - LTP
which equals:
VH = 2BVsat

102. Comparator Comparators with Hysteresis or Schmitt Trigger
Inverting Schmitt trigger
Lab experiment:
a) Design and construct a Schmitt trigger using Op-Amp for given UTP and LTP values and demonstrate its working. (Wired Experiment)
b) Design and implement a Schmitt trigger using Op- Amp using a simulation package for two sets of UTP and LTP values and demonstrate its working. (Simulation Experiment)

103. Comparator Comparators with Hysteresis or Schmitt Trigger
Non-Inverting Schmitt trigger

104. Comparator Comparators with Hysteresis or Schmitt Trigger
Non-Inverting Schmitt trigger
Assume that the output is negatively saturated. The feedback voltage will hold the output in negative saturation until the input voltage becomes slightly more positive than UTP. When this happens, the output switches from negative to positive saturation.
Once in positive saturation, the output stays there until the input voltage becomes slightly less than LTP. Then, the output can change back to the negative state.

105. Comparator Window Comparator
An ordinary comparator indicates when the input voltage exceeds a certain limit or threshold.
A window comparator (also called a double-ended limit detector) detects when the input voltage is between two limits called the window. To create a window comparator, will use two comparators with different thresholds.

106. Comparator Window Comparator
Low Output between Limits

107. Comparator Window Comparator
Low Output between Limits
Circuit shows a window comparator that can produce a low output voltage when the input voltage is between a lower and an upper limit.
When Vin is less than LTP or greater than UTP, the output is high. When Vin is between LTP and UTP, the output is low.
Operation:
When Vin < LTP, comparator A1 has a positive output and A2 has a negative output. Diode D1 is on and D2 is off. Therefore, the output voltage is high.
Similarly, when Vin > UTP, comparator A1 has a negative output and A2 has a positive output. Diode D1 is off, D2 is on, and the output voltage is high.
When LTP < Vin < UTP, A1 has a negative output, A2 has a negative output, D1 is off, D2 is off, and the output voltage is low.

108. Active Filters
An electric filter is often a frequency selective circuit that passes a specified band of frequency and blocks or attenuates signals of frequencies outside this band.
Active filters employs transistor or op-amp in addition to resistor and capacitor.
RC network are used for filter.
The most commonly used filters are follows:
Low pass filters
High pass filter
Band pass filter
Band reject filter.
All pass filter
Next slide shows the frequency response characteristics of the five types of filter. The ideal response is shown by dashed line. While the solid lines indicates the practical filter response.

109. Active Filters

110. Active Filters
A filter that provides a constant output from dc up to a cut-off frequency fH and then passes no signal above that frequency is called an ideal low-pass filter.
A filter that provides or passes signals above a cutoff frequency fL is a high-pass filter, as shown in previous slide.
When the filter circuit passes signals that are above one ideal cutoff frequency (fL) and below a second cutoff frequency, (fH) it is called a bandpass filter.
Two types of filters
First Order Filter – One capacitor used
Second Order Filter – Two or more capacitor used

111. Active Filters Attenuation refers to a loss of signal.
The order of a passive filter equals the number of inductors and capacitors in the filter.
The quality factor is the measure of “frequency selectivity" of a filter circuit.
High the Q narrower the bandwidth
Lower the Q wider the bandwidth

112. Active Filters- Low-pass filter
Non-Inverting unity gain
It is nothing more than an RC lag circuit and a voltage follower. The voltage gain is: Av = 1.
When the frequency increases above the cutoff frequency, the capacitive reactance decreases and reduces the noninverting input voltage.
Since the R1C1 lag circuit is outside the feedback loop, the output voltage rolls off. As the frequency approaches infinity, the capacitor becomes a short and there is zero input voltage.

113. Active Filters- Low-pass filter
Non-Inverting with voltage gain
Although it has two additional resistors, it has the advantage of voltage gain.

114. Active Filters- Low-pass filter
Inverting with voltage gain
As the frequency increases, the capacitive reactance decreases and reduces the impedance of the feedback branch. This implies less voltage gain.
As the frequency approaches infinity, the capacitor becomes a short and there is no voltage gain.

115. Active Filters- High-pass filter
Noninverting unity gain
When the frequency decreases below the cutoff frequency, the capacitive reactance increases and reduces the noninverting input voltage.
Since the R1C1 circuit is outside the feedback loop, the output voltage rolls off. As the frequency approaches zero, the capacitor becomes an open and there is zero input voltage.

116. Active Filters- High-pass filter
Non-Inverting with voltage gain

117. Active Filters- High-pass filter
Inverting with voltage gain

118. Active Filters- Second Order Filter Low Pass/High Pass Filter
Generalized form of second order filter
If Z1=Z2=R and Z3=Z4=C get second order low pass filter
If Z1=Z2=C and Z3=Z4=R get second order high pass filter

119. Active Filters- Band-pass Filter
Two types of band pass filter
Wide band pass filter
Narrow band pass filter

120. Active Filters- Band-pass Filter
Wide Band Pass Filters
Cascade of low-pass and high-pass filter

121. Active Filters- Band-pass Filter
Narrow Band Pass Filters
In the circuit the input signal goes to the inverting input rather than the noninverting input. Also the circuit has two feedback paths, one through a capacitor and another through a resistor.

122. Active Filters- Band-pass Filter
Narrow Band Pass Filters
At low frequencies, the capacitors appear to be open. Therefore, the input signal cannot reach the op amp, and the output is zero.
At high frequencies, the capacitors appear to be shorted. In this case, the voltage gain is zero because the feedback capacitor has zero impedance.
Between the low and high extremes in frequency, there is a band of frequencies where the circuit acts like an inverting amplifier.

123. Active Filters- Band-Reject/Stop Filter
Two types of Band Reject Filter:
Wide/Broad Band Reject filter
Narrow/Notch Band Reject Filter
Summing together the output of the low pass and high pass filter produces broad reject filter.

124. Active Filters- Band-Reject/Stop/Notch Filter
Narrow/Notch Band Reject Filter

125. Active Filters- Band-Reject/Stop/Notch Filter
Narrow/Notch Band Reject Filter
At low frequencies, all capacitors are open. As a result, all the input signal reaches the noninverting input of op- amp and passes to the output.
At very high frequencies, the capacitors are shorted. Again, all the input signal reaches the noninverting input and passes to the output.
Between the low and high extremes in frequency the feedback signal returns with the correct amplitude and phase to attenuate the signal on the noninverting input. Because of this, the output voltage drops to a very low value.

126. Active Filters- All Pass Filter
Also called phase filter because the filter shifts the phase of the output signal without changing the magnitude.

127. Active Filters- All Pass Filter
All-pass lag filter
R<< (1/2πfC) then phase shift Ø= 0º
R>> (1/2πfC) then phase shift Ø= -180º
R= (1/2πfC) then phase shift Ø= -90º
Where f is the input frequecy

128. Active Filters- All Pass Filter
All-pass lead filter
R<< (1/2πfC )then phase shift Ø= 90º
R>> (1/2πfC )then phase shift Ø= 180º
R= (1/2πfC) then phase shift Ø= 0º
Where f is the input frequecy

129. Non-Linear Amplifier
In this amplifier the gain value is non-linear function of the amplitude of the input signal.
The gain may be large for weak signal and very small for large signal this can achieved using non- linear device such as PN junction diode as shown below. Also called log amplifier.

130. Non-Linear Amplifier Working:
For small value of input signal, diodes act as open circuit and the gain is high due to minimum feedback.
When the amplitude of input signal is large, diodes offer very small resistance and thus gain is low.

131. Relaxation Oscillator

132. Relaxation Oscillator
In circuit, there is no input signal.
Nevertheless, the circuit produces a rectangular output signal. This output is a square wave that swings between –Vsat and +Vsat. How is this possible?
Assume that the output is in positive saturation. Because of feedback resistor R, the capacitor will charge exponentially toward +Vsat, as shown in waveform. But the capacitor voltage never reaches +Vsat because the voltage crosses the UTP. When this happens, the output square wave switches to –Vsat.
With the output now in negative saturation, the capacitor discharges, as shown in waveform. When the capacitor voltage crosses through zero, the capacitor starts charging negatively toward –Vsat. When the capacitor voltage crosses the LTP, the output square wave switches back to +Vsat. The cycle then repeats.

133. Relaxation Oscillator
Lab Experiment:
a) Design and construct a rectangular waveform generator (Op-Amp relaxation oscillator) for given frequency and demonstrate its working. (Wired Experiment)
b) Design and implement a rectangular waveform generator (Op-Amp relaxation oscillator) using a simulation package and demonstrate the change in frequency when all resistor values are doubled. (Simulation Experiment)

134. Current-To-Voltage Converter
Also called Transimpedance amplifier
From Fig-1Voltage gain of the amplifier is
𝐴=− 𝑅𝑓 𝑅1 or 𝑉𝑂𝑢𝑡 𝑉𝑖𝑛 =− 𝑅𝑓 𝑅1
𝑉𝑜𝑢𝑡=− 𝑉𝑖𝑛 𝑅1 𝑅𝑓 (1)
Fig-1can also be represent as Fig-2
From Fig-2 circuit
𝑖𝑖𝑛= 𝑉𝑖𝑛 𝑅1
So equation (1) becomes
𝑉𝑜𝑢𝑡=−𝑖𝑖𝑛𝑅𝑓
So input current converted to output voltage.
Application: DAC, Sensing Current from photodetector
Fig-1
Fig-2

135. Voltage-To-Current Converter
Also called Transconductance amplifier.
Apply KVL at input side
𝑉𝑖𝑛 −𝑖𝑜𝑢𝑡𝑅1=0
𝑉𝑖𝑛=𝑖𝑜𝑢𝑡𝑅1
𝑖𝑜𝑢𝑡= 𝑉𝑖𝑛 𝑅1
Form equation the input voltage is converted into output current.
Application: DC and AC voltmeter, LED, Zener Diode tester.

136. Wave Shaping Circuits

137. Integrated Circuit(IC) Multivibrators
A multivibrator circuit oscillates between a “HIGH” state and a “LOW” state producing a continuous output.
It generates square, rectangular, pulse waveforms, also called nonlinear oscillators or function generators.
There are basically three types of clock pulse generation circuits:
Astable – A free-running multivibrator that has NO stable states but switches continuously between two states this action produces a train of square/rectangular wave pulses at a fixed frequency.
Monostable – A one-shot multivibrator that has only ONE stable state and is triggered externally with it returning back to its first stable state.
Bistable – A flip-flop that has TWO stable states that produces a single pulse either positive or negative in value.

138. Integrated Circuit(IC) Multivibrators

139. Integrated Circuit(IC) Multivibrators
The NE555 (also LM555, CA555) is a widely used IC timer, a circuit that can run in either of two modes: monostable (one stable state) or astable (no stable states).

140. Integrated Circuit(IC) Multivibrators
Functional Block Diagram of IC 555
The 555 timer contains a voltage divider, two comparators, an RS flip-flop, and an npntransistor.
Since the voltage divider has equal resistors, the top comparator (C1) has a trip point of:
𝑼𝑻𝑷= 𝟐 𝟑 𝑽𝑪𝑪
The lower comparator (C2) has a trip point of:
𝑳𝑻𝑷= 𝟏 𝟑 𝑽𝑪𝑪

141. Integrated Circuit(IC) Multivibrators
Pin-1 (Ground)
Pin-2 (Trigger) Is connected to the lower comparator. The trigger voltage that is used for the monostable operation of the 555 timer. When the timer is inactive, the trigger voltage is high. When the trigger voltage falls to less than the LTP, the lower comparator (C2) produces a high output.
Pin-3 (Output)
Pin-4 (Reset) Pin 4 may be used to reset the output voltage to zero. If Pin 4 is not in used so it should connected to +VCC.
Pin-5 (Control) Pin 5 may be used to control the output frequency when the 555 timer is used in the astable mode. If not in use then pin 5 is bypassed to ground through a capacitor
Pin-6 (Threshold) Pin 6 is connected to the upper comparator. The voltage on pin 6 is called the threshold. This voltage comes from external components not shown. When the threshold voltage is greater than the UTP, the upper comparator (C1) has a high output.
Pin-7 (Discharge) To discharge the external connected capacitor when transistor in ON.
Pin-8 (+VCC)

142. Integrated Circuit(IC) Multivibrators
SR Flip-Flop
Duty cycle (D) is the proportion of time during which the device is operated.  
In terms of square wave signal it defines the percentage of time for which signal is at logic high level.
For square wave it can be calculated as (high time / (high time + low time))
Duty cycle of 50% means that the low time and high time of the signal is same. S R Q 𝑸
No Change 1
Invalid

143. Integrated Circuit(IC) Multivibrators Astable Operation of the 555 Timer
Circuit Diagram
Charge time (High Time)
𝑡𝑐=0.693 𝑅1+𝑅2 𝐶
Discharge time (Low Time)
𝑡𝑑=0.693𝑅2𝐶
Total Time period T is
𝑇=𝑡𝑐+𝑡𝑑
The frequency is given by
𝑓𝑂= 1 𝑇
The duty cycle is
%𝐷= 𝑡𝑐 𝑇

144. Integrated Circuit(IC) Multivibrators Astable Operation of the 555 Timer
Capacitor and output waveforms

145. Integrated Circuit(IC) Multivibrators Astable Operation of the 555 Timer
Capacitor and output waveforms
When output 𝑄 = High, so the transistor is OFF and capacitor C starts charging through R1 and R2 till reaches to UTP

146. Integrated Circuit(IC) Multivibrators Astable Operation of the 555 Timer
Capacitor and output waveforms
When output 𝑄 = Low, so the transistor is ON and capacitor C starts discharging through R2 till reaches to LTP

147. Integrated Circuit(IC) Multivibrators Astable Operation of the 555 Timer
When Q is low, the transistor is cut off and the capacitor is charging through R1 and R2 resistance. Because of this, the charging time constant is (R1+R2)C. As the capacitor charges, the threshold voltage (pin 6) increases. Eventually, the threshold voltage exceeds 2 3 VCC. Then, the upper comparator sets the flip-flop.
With Q high, the transistor saturates and grounds pin 7. The capacitor now discharges through R2. Therefore, the discharging time constant is R2C. When the capacitor voltage drops to slightly less than 1 3 VCC, the lower comparator resets the flip-flop.
The output is a rectangular wave that swings between 0 and VCC. Since the charging time constant is longer than the discharging time constant, the output is nonsymmetrical. Depending on resistances R1 and R2, the duty cycle is between 50 and 100 percent.
When R1 is much smaller than R2, the duty cycle approaches 50 percent. Conversely, when R1 is much greater than R2, the duty cycle approaches 100 percent.
To make the duty cycle to become less than 50 percent. By placing a diode in parallel with R2 (anode connected to pin 7), the capacitor will effectively charge through R1 and the diode. The capacitor will discharge through R2.

148. Integrated Circuit(IC) Multivibrators Astable Operation of the 555 Timer
Lab Experiment:
Design and implement an Astable multivibrator circuit using 555 timer for a given frequency and duty cycle.

149. Integrated Circuit(IC) Multivibrators Monostable Operation of the 555 Timer
Circuit Diagram
Pulse Width is
W=1.1RC
The circuit has an external resistor R and a capacitor C.
The voltage across the capacitor is used for the threshold voltage to pin 6.
When the trigger arrives at pin 2, the circuit produces a rectangular output pulse from pin 3.

150. Integrated Circuit(IC) Multivibrators Monostable Operation of the 555 Timer

151. Integrated Circuit(IC) Multivibrators Monostable Operation of the 555 Timer
Initially, the Q output of the RS flip-flop is high. This turn ON the transistor and the capacitor discharge to ground through pin 7. The circuit will remain in this state until a trigger arrives at pin 2.
When the trigger input falls to slightly less than 1 3 VCCthe lower comparator resets the flip-flop. Since Q has changed to low, the transistor goes OFF, allowing the capacitor to charge. At this time, 𝑄 has changed to high.
The capacitor now charges exponentially through R as shown in waveform. When the capacitor voltage is slightly greater than VCC, the upper comparator sets the flip-flop. The high Q turns ON the transistor, which discharges the capacitor almost instantly. At the same instant, 𝑄 returns to the low state and the output pulse ends.
𝑄 remains low until another input trigger arrives.